mirror of https://github.com/YosysHQ/yosys.git
Add "chformal -assert2assume" and friends
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@ -55,9 +55,20 @@ struct ChformalPass : public Pass {
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log(" -skip <N>\n");
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log(" ignore activation of the constraint in the first <N> clock cycles\n");
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log("\n");
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log(" -assert2assume\n");
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log(" -assume2assert\n");
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log(" -live2fair\n");
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log(" -fair2live\n");
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log(" change the roles of cells as indicated. this options can be combined\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool assert2assume = false;
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bool assume2assert = false;
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bool live2fair = false;
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bool fair2live = false;
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pool<IdString> constr_types;
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char mode = 0;
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int mode_arg;
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@ -103,6 +114,26 @@ struct ChformalPass : public Pass {
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mode_arg = atoi(args[++argidx].c_str());
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") {
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assert2assume = true;
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mode = 'c';
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-assume2assert") {
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assume2assert = true;
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mode = 'c';
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-live2fair") {
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live2fair = true;
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mode = 'c';
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-fair2live") {
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fair2live = true;
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mode = 'c';
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -231,6 +262,19 @@ struct ChformalPass : public Pass {
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for (auto cell : constr_cells)
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cell->setPort("\\EN", module->LogicAnd(NEW_ID, en, cell->getPort("\\EN")));
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}
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else
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if (mode == 'c')
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{
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for (auto cell : constr_cells)
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if (assert2assume && cell->type == "$assert")
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cell->type = "$assume";
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else if (assume2assert && cell->type == "$assume")
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cell->type = "$assert";
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else if (live2fair && cell->type == "$live")
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cell->type = "$fair";
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else if (fair2live && cell->type == "$fair")
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cell->type = "$live";
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}
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}
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}
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} ChformalPass;
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