mirror of https://github.com/YosysHQ/yosys.git
Improved handling of techmap special wires
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@ -78,7 +78,7 @@ static TechmapWires techmap_find_special_wires(RTLIL::Module *module)
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record.value = it.second;
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result[p].push_back(record);
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it.second->attributes["\\keep"] = RTLIL::Const(1);
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it.second->attributes["\\_techmap_attr_"] = RTLIL::Const(1);
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it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
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}
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}
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@ -112,6 +112,8 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module,
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (it.second->get_bool_attribute("\\_techmap_special_"))
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w->attributes.clear();
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module->wires[w->name] = w;
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design->select(module, w);
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}
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