riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Renamed "placeholder" to "blackbox"

This commit is contained in:
Clifford Wolf 2013-11-22 15:01:12 +01:00
parent c854ad2e7e
commit 295e352ba6
12 changed files with 27 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
README
View File

@ -248,11 +248,11 @@ Verilog Attributes and non-standard features
temporary variable within an always block. This is mostly used internally
by yosys to synthesize verilog functions and access arrays.
- The "placeholder" attribute on modules is used to mark empty stub modules
- The "blackbox" attribute on modules is used to mark empty stub modules
that have the same ports as the real thing but do not contain information
on the internal configuration. This modules are only used by the synthesis
passes to identify input and output ports of cells. The verilog backend
also does not output placeholder modules on default.
also does not output blackbox modules on default.
- The "keep" attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that

2
backends/blif/blif.cc
View File

@ -300,7 +300,7 @@ struct BlifBackend : public Backend {
for (auto module_it : design->modules)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (module->processes.size() != 0)

6
backends/edif/edif.cc
View File

@ -121,7 +121,7 @@ struct EdifBackend : public Backend {
for (auto module_it : design->modules)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (top_module_name.empty())
@ -135,7 +135,7 @@ struct EdifBackend : public Backend {
for (auto cell_it : module->cells)
{
RTLIL::Cell *cell = cell_it.second;
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) {
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
lib_cell_ports[cell->type];
for (auto p : cell->connections) {
if (p.second.width > 1)
@ -233,7 +233,7 @@ struct EdifBackend : public Backend {
fprintf(f, " (technology (numberDefinition))\n");
for (auto module : sorted_modules)
{
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
SigMap sigmap(module);

2
backends/intersynth/intersynth.cc
View File

@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend {
RTLIL::Module *module = module_it.second;
SigMap sigmap(module);
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
continue;

4
backends/spice/spice.cc
View File

@ -57,7 +57,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
if (design->modules.count(cell->type) == 0)
{
log("Warning: no (placeholder) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
@ -178,7 +178,7 @@ struct SpiceBackend : public Backend {
for (auto module_it : design->modules)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (module->processes.size() != 0)

14
backends/verilog/verilog_backend.cc
View File

@ -941,9 +941,9 @@ struct VerilogBackend : public Backend {
log(" without this option all internal cells are converted to verilog\n");
log(" expressions.\n");
log("\n");
log(" -placeholders\n");
log(" usually modules with the 'placeholder' attribute are ignored. with\n");
log(" this option set only the modules with the 'placeholder' attribute\n");
log(" -blackboxes\n");
log(" usually modules with the 'blackbox' attribute are ignored. with\n");
log(" this option set only the modules with the 'blackbox' attribute\n");
log(" are written to the output file.\n");
log("\n");
log(" -selected\n");
@ -960,7 +960,7 @@ struct VerilogBackend : public Backend {
attr2comment = false;
noexpr = false;
bool placeholders = false;
bool blackboxes = false;
bool selected = false;
reg_ct.clear();
@ -988,8 +988,8 @@ struct VerilogBackend : public Backend {
noexpr = true;
continue;
}
if (arg == "-placeholders") {
placeholders = true;
if (arg == "-blackboxes") {
blackboxes = true;
continue;
}
if (arg == "-selected") {
@ -1002,7 +1002,7 @@ struct VerilogBackend : public Backend {
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if (it->second->get_bool_attribute("\\placeholder") != placeholders)
if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
continue;
if (selected && !design->selected_whole_module(it->first)) {
if (design->selected_module(it->first))

2
frontends/ast/ast.cc
View File

@ -720,7 +720,7 @@ static AstModule* process_module(AstNode *ast)
delete child;
}
ast->children.swap(new_children);
ast->attributes["\\placeholder"] = AstNode::mkconst_int(1, false);
ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
}
ignoreThisSignalsInInitial = RTLIL::SigSpec();

2
frontends/verilog/verilog_frontend.cc
View File

@ -90,7 +90,7 @@ struct VerilogFrontend : public Frontend {
log(" do not run the pre-processor\n");
log("\n");
log(" -lib\n");
log(" only create empty placeholder modules\n");
log(" only create empty blackbox modules\n");
log("\n");
log(" -noopt\n");
log(" don't perform basic optimizations (such as const folding) in the\n");

4
passes/cmds/add.cc
View File

@ -73,7 +73,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->modules.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_bool_attribute("\\placeholder"))
if (mod->get_bool_attribute("\\blackbox"))
continue;
if (it.second->connections.count(name) > 0)
continue;
@ -144,7 +144,7 @@ struct AddPass : public Pass {
RTLIL::Module *module = mod.second;
if (!design->selected_whole_module(module->name))
continue;
if (module->get_bool_attribute("\\placeholder"))
if (module->get_bool_attribute("\\blackbox"))
continue;
if (command == "wire")

6
passes/cmds/show.cc
View File

@ -477,8 +477,8 @@ struct ShowWorker
if (!design->selected_module(module->name))
continue;
if (design->selected_whole_module(module->name)) {
if (module->get_bool_attribute("\\placeholder")) {
log("Skipping placeholder module %s.\n", id2cstr(module->name));
if (module->get_bool_attribute("\\blackbox")) {
log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
if (module->cells.empty() && module->connections.empty() && module->processes.empty()) {
@ -617,7 +617,7 @@ struct ShowPass : public Pass {
if (format != "ps") {
int modcount = 0;
for (auto &mod_it : design->modules) {
if (mod_it.second->get_bool_attribute("\\placeholder"))
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
continue;

6
passes/hierarchy/hierarchy.cc
View File

@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;
mod->attributes["\\placeholder"] = RTLIL::Const(1);
mod->attributes["\\blackbox"] = RTLIL::Const(1);
design->modules[mod->name] = mod;
for (auto &decl : ports) {
@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
}
if (cell->parameters.size() == 0)
continue;
if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder"))
if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
continue;
RTLIL::Module *mod = design->modules[cell->type];
cell->type = mod->derive(design, cell->parameters);
@ -280,7 +280,7 @@ struct HierarchyPass : public Pass {
log(" use the specified top module to built a design hierarchy. modules\n");
log(" outside this tree (unused modules) are removed.\n");
log("\n");
log("In -generate mode this pass generates placeholder modules for the given cell\n");
log("In -generate mode this pass generates blackbox modules for the given cell\n");
log("types (wildcards supported). For this the design is searched for cells that\n");
log("match the given types and then the given port declarations are used to\n");
log("determine the direction of the ports. The syntax for a port declaration is:\n");

2
passes/techmap/dfflibmap.cc
View File

@ -498,7 +498,7 @@ struct DfflibmapPass : public Pass {
logmap_all();
for (auto &it : design->modules)
if (design->selected(it.second) && !it.second->get_bool_attribute("\\placeholder"))
if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
dfflibmap(design, it.second);
cell_mappings.clear();