mirror of https://github.com/YosysHQ/yosys.git
Extract $alu cells in alumacc
This commit is contained in:
Clifford Wolf
parent
7b16c63101
commit
0df1d9ad72
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@ -33,10 +33,78 @@ struct AlumaccWorker
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int users;
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};
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struct alunode_t
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{
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std::vector<RTLIL::Cell*> cells;
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RTLIL::SigSpec a, b, c, y;
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std::vector<std::tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp;
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bool is_signed, invert_b;
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RTLIL::Cell *alu_cell;
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RTLIL::SigSpec cached_lt, cached_gt, cached_eq, cached_ne;
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RTLIL::SigSpec cached_cf, cached_of, cached_sf;
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RTLIL::SigSpec get_lt() {
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if (SIZE(cached_lt) == 0)
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cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
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return cached_lt;
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}
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RTLIL::SigSpec get_gt() {
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if (SIZE(cached_gt) == 0)
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cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()));
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return cached_gt;
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}
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RTLIL::SigSpec get_eq() {
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if (SIZE(cached_eq) == 0)
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cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"));
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return cached_eq;
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}
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RTLIL::SigSpec get_ne() {
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if (SIZE(cached_ne) == 0)
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cached_ne = alu_cell->module->Not(NEW_ID, get_eq());
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return cached_ne;
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}
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RTLIL::SigSpec get_cf() {
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if (SIZE(cached_cf) == 0) {
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cached_cf = alu_cell->getPort("\\CO");
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log_assert(SIZE(cached_cf) >= 1);
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cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[SIZE(cached_cf)-1]);
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}
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return cached_cf;
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}
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RTLIL::SigSpec get_of() {
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if (SIZE(cached_of) == 0) {
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cached_of = {alu_cell->getPort("\\CO"), alu_cell->getPort("\\CI")};
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log_assert(SIZE(cached_of) >= 2);
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cached_of = alu_cell->module->Xor(NEW_ID, cached_of[SIZE(cached_of)-1], cached_of[SIZE(cached_of)-2]);
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}
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return cached_of;
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}
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RTLIL::SigSpec get_sf() {
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if (SIZE(cached_sf) == 0) {
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cached_sf = alu_cell->getPort("\\Y");
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cached_sf = cached_sf[SIZE(cached_sf)-1];
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}
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return cached_sf;
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}
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};
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std::map<RTLIL::SigBit, int> bit_users;
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std::map<RTLIL::SigSpec, maccnode_t*> sig_macc;
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std::map<RTLIL::SigSig, std::set<alunode_t*>> sig_alu;
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int macc_counter, alu_counter;
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AlumaccWorker(RTLIL::Module *module) : module(module), sigmap(module) { }
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AlumaccWorker(RTLIL::Module *module) : module(module), sigmap(module)
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{
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macc_counter = 0;
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alu_counter = 0;
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}
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void count_bit_users()
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{
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@ -158,12 +226,96 @@ struct AlumaccWorker
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}
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}
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void macc_to_alu()
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{
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std::set<maccnode_t*> delete_nodes;
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for (auto &it : sig_macc)
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{
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auto n = it.second;
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RTLIL::SigSpec A, B, C = n->macc.bit_ports;
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bool a_signed = false, b_signed = false;
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bool subtract_b = false;
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alunode_t *alunode;
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for (auto &port : n->macc.ports)
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if (SIZE(port.in_b) > 0) {
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goto next_macc;
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} else if (SIZE(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
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C.append(port.in_a);
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} else if (SIZE(A) || port.do_subtract) {
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if (SIZE(B))
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goto next_macc;
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B = port.in_a;
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b_signed = port.is_signed;
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subtract_b = port.do_subtract;
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} else {
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if (SIZE(A))
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goto next_macc;
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A = port.in_a;
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a_signed = port.is_signed;
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}
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if (!a_signed || !b_signed) {
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if (SIZE(A) == SIZE(n->y))
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a_signed = false;
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if (SIZE(B) == SIZE(n->y))
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b_signed = false;
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if (a_signed != b_signed)
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goto next_macc;
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}
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if (SIZE(A) == 0 && SIZE(C) > 0) {
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A = C[0];
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C.remove(0);
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}
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if (SIZE(B) == 0 && SIZE(C) > 0) {
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B = C[0];
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C.remove(0);
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}
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if (subtract_b)
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C.append(RTLIL::S1);
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if (SIZE(C) > 1)
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goto next_macc;
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if (!subtract_b && B < A)
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std::swap(A, B);
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log(" creating $alu model for $macc %s.\n", log_id(n->cell));
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alunode = new alunode_t;
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alunode->cells.push_back(n->cell);
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alunode->is_signed = a_signed;
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alunode->invert_b = subtract_b;
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alunode->a = A;
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alunode->b = B;
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alunode->c = C;
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alunode->y = n->y;
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sig_alu[RTLIL::SigSig(A, B)].insert(alunode);
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delete_nodes.insert(n);
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next_macc:;
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}
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for (auto n : delete_nodes) {
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sig_macc.erase(n->y);
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delete n;
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}
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}
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void replace_macc()
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{
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macc_counter += SIZE(sig_macc);
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for (auto &it : sig_macc)
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{
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auto n = it.second;
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auto cell = module->addCell(NEW_ID, "$macc");
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log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
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n->macc.to_cell(cell);
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cell->setPort("\\Y", n->y);
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cell->fixup_parameters();
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@ -174,6 +326,144 @@ struct AlumaccWorker
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sig_macc.clear();
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}
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void extract_cmp_alu()
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{
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std::vector<RTLIL::Cell*> lge_cells, eq_cells;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("$lt", "$le", "$ge", "$gt"))
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lge_cells.push_back(cell);
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if (cell->type.in("$eq", "$eqx", "$ne", "$nex"))
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eq_cells.push_back(cell);
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}
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for (auto cell : lge_cells)
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{
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log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
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bool cmp_less = cell->type.in("$lt", "$le");
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bool cmp_equal = cell->type.in("$le", "$ge");
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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RTLIL::SigSpec A = sigmap(cell->getPort("\\A"));
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RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
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RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
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if (B < A) {
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cmp_less = !cmp_less;
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std::swap(A, B);
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}
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alunode_t *n = nullptr;
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for (auto node : sig_alu[RTLIL::SigSig(A, B)])
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if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
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n = node;
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break;
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}
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if (n == nullptr) {
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n = new alunode_t;
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n->a = A;
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n->b = B;
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n->c = RTLIL::S1;
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n->y = module->addWire(NEW_ID, std::max(SIZE(A), SIZE(B)));
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n->is_signed = is_signed;
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n->invert_b = true;
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sig_alu[RTLIL::SigSig(A, B)].insert(n);
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log(" new $alu\n");
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} else {
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log(" merged with %s.\n", log_id(n->cells.front()));
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}
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n->cells.push_back(cell);
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n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y));
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}
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for (auto cell : eq_cells)
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{
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bool cmp_equal = cell->type.in("$eq", "$eqx");
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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RTLIL::SigSpec A = sigmap(cell->getPort("\\A"));
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RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
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RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
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if (B < A)
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std::swap(A, B);
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alunode_t *n = nullptr;
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for (auto node : sig_alu[RTLIL::SigSig(A, B)])
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if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
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n = node;
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break;
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}
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if (n != nullptr) {
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log(" creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
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n->cells.push_back(cell);
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n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, Y));
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}
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}
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}
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void replace_alu()
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{
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alu_counter += SIZE(sig_alu);
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for (auto &it1 : sig_alu)
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for (auto n : it1.second)
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{
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n->alu_cell = module->addCell(NEW_ID, "$alu");
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log(" creating $alu cell for ");
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for (int i = 0; i < SIZE(n->cells); i++)
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log("%s%s", i ? ", ": "", log_id(n->cells[i]));
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log(": %s\n", log_id(n->alu_cell));
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RTLIL::Wire *x = module->addWire(NEW_ID, SIZE(n->y));
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RTLIL::Wire *co = module->addWire(NEW_ID, SIZE(n->y));
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n->alu_cell->setPort("\\A", n->a);
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n->alu_cell->setPort("\\B", n->b);
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n->alu_cell->setPort("\\CI", SIZE(n->c) ? n->c : RTLIL::S0);
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n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0);
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n->alu_cell->setPort("\\Y", n->y);
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n->alu_cell->setPort("\\X", x);
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n->alu_cell->setPort("\\CO", co);
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n->alu_cell->fixup_parameters();
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for (auto &it : n->cmp)
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{
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bool cmp_lt = std::get<0>(it);
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bool cmp_gt = std::get<1>(it);
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bool cmp_eq = std::get<2>(it);
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bool cmp_ne = std::get<3>(it);
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RTLIL::SigSpec cmp_y = std::get<4>(it);
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RTLIL::SigSpec sig;
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if (cmp_lt) sig.append(n->get_lt());
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if (cmp_gt) sig.append(n->get_gt());
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if (cmp_eq) sig.append(n->get_eq());
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if (cmp_ne) sig.append(n->get_ne());
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if (SIZE(sig) > 1)
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sig = module->ReduceOr(NEW_ID, sig);
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sig.extend(SIZE(cmp_y));
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module->connect(cmp_y, sig);
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}
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for (auto c : n->cells)
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module->remove(c);
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delete n;
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}
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sig_alu.clear();
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}
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void run()
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{
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log("Extracting $alu and $macc cells in module %s:\n", log_id(module));
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@ -181,7 +471,12 @@ struct AlumaccWorker
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count_bit_users();
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extract_macc();
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merge_macc();
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macc_to_alu();
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replace_macc();
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extract_cmp_alu();
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replace_alu();
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log(" created %d $alu and %d $macc cells.\n", alu_counter, macc_counter);
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}
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};
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