mirror of https://github.com/YosysHQ/yosys.git
Fix abc's remap_name to not ignore [^0-9] when extracting sid
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@ -331,19 +331,23 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
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{
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std::string abc_sname = abc_name.substr(1);
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if (abc_sname.substr(0, 5) == "ys__n") {
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int sid = std::stoi(abc_sname.substr(5));
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bool inv = abc_sname.back() == 'v';
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for (auto sig : signal_list) {
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if (sig.id == sid && sig.bit.wire != nullptr) {
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std::stringstream sstr;
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sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1);
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if (sig.bit.wire->width != 1)
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sstr << "[" << sig.bit.offset << "]";
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if (inv)
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sstr << "_inv";
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if (orig_wire != nullptr)
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*orig_wire = sig.bit.wire;
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return sstr.str();
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if (inv) abc_sname.pop_back();
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abc_sname.erase(0, 5);
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if (abc_sname.find_last_not_of("012345689") == std::string::npos) {
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int sid = std::stoi(abc_sname);
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for (auto sig : signal_list) {
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if (sig.id == sid && sig.bit.wire != nullptr) {
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std::stringstream sstr;
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sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1);
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if (sig.bit.wire->width != 1)
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sstr << "[" << sig.bit.offset << "]";
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if (inv)
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sstr << "_inv";
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if (orig_wire != nullptr)
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*orig_wire = sig.bit.wire;
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return sstr.str();
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}
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}
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}
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}
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