mirror of https://github.com/YosysHQ/yosys.git
Throw out unused code inherited from abc
This commit is contained in:
Eddie Hung
parent
887c31f33b
commit
a379234f56
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@ -467,48 +467,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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{
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log_header(design, "Executing ABC9.\n");
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std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
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f = fopen(buffer.c_str(), "wt");
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if (f == NULL)
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
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fprintf(f, "GATE ONE 1 Y=CONST1;\n");
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
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if (enabled_gates.empty() || enabled_gates.count("AND"))
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
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if (enabled_gates.empty() || enabled_gates.count("NAND"))
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
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if (enabled_gates.empty() || enabled_gates.count("OR"))
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
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if (enabled_gates.empty() || enabled_gates.count("NOR"))
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
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if (enabled_gates.empty() || enabled_gates.count("XOR"))
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
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if (enabled_gates.empty() || enabled_gates.count("XNOR"))
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
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if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
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if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
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if (enabled_gates.empty() || enabled_gates.count("AOI3"))
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
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if (enabled_gates.empty() || enabled_gates.count("OAI3"))
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
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if (enabled_gates.empty() || enabled_gates.count("AOI4"))
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
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if (enabled_gates.empty() || enabled_gates.count("OAI4"))
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
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if (enabled_gates.empty() || enabled_gates.count("MUX"))
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
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if (map_mux4)
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fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
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if (map_mux8)
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fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
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if (map_mux16)
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fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
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fclose(f);
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std::string buffer;
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if (!lut_costs.empty()) {
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buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
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f = fopen(buffer.c_str(), "wt");
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@ -680,161 +639,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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continue;
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}
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cell_stats[RTLIL::unescape_id(c->type)]++;
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if (c->type == "\\ZERO" || c->type == "\\ONE") {
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RTLIL::SigSig conn;
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conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
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conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
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module->connect(conn);
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continue;
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}
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if (c->type == "\\BUF") {
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RTLIL::SigSig conn;
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conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
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conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
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module->connect(conn);
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continue;
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}
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if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" ||
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c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") {
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
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cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
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cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
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continue;
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}
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if (c->type == "\\MUX") {
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
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cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
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cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
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cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
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continue;
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}
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if (c->type == "\\MUX4") {
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_");
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
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cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
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cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
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cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
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cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
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continue;
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}
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if (c->type == "\\MUX8") {
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_");
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
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cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
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cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
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cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
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cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
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cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
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cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
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cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
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cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
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cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
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continue;
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}
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if (c->type == "\\MUX16") {
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_");
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
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cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
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cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
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cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
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cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
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cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
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cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)]));
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cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)]));
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cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)]));
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cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)]));
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cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)]));
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cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)]));
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cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)]));
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cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)]));
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cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
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cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
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cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
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cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)]));
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cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
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continue;
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}
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if (c->type == "\\AOI3" || c->type == "\\OAI3") {
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
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cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
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cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
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cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
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continue;
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}
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if (c->type == "\\AOI4" || c->type == "\\OAI4") {
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
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cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
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cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
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continue;
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}
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if (c->type == "\\DFF") {
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log_assert(clk_sig.size() == 1);
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RTLIL::Cell *cell;
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if (en_sig.size() == 0) {
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cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
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} else {
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log_assert(en_sig.size() == 1);
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cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
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cell->setPort("\\E", en_sig);
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}
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
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cell->setPort("\\C", clk_sig);
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continue;
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}
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}
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else
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cell_stats[RTLIL::unescape_id(c->type)]++;
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cell_stats[RTLIL::unescape_id(c->type)]++;
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if (c->type == "\\_const0_" || c->type == "\\_const1_") {
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RTLIL::SigSig conn;
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conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
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conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
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module->connect(conn);
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continue;
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}
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if (c->type == "\\_dff_") {
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log_assert(clk_sig.size() == 1);
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RTLIL::Cell *cell;
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if (en_sig.size() == 0) {
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cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
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} else {
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log_assert(en_sig.size() == 1);
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cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
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cell->setPort("\\E", en_sig);
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}
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
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cell->setPort("\\C", clk_sig);
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continue;
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}
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RTLIL::Cell* cell;
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if (c->type == "$lut") {
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if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
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SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
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@ -846,7 +653,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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else
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log_assert(erased_boxes.count(c->name));
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cell = module->addCell(remap_name(c->name), c->type);
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RTLIL::Cell* cell = module->addCell(remap_name(c->name), c->type);
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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cell->parameters = c->parameters;
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for (auto &conn : c->connections()) {
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@ -893,22 +700,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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for (auto &it : cell_stats)
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log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
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int in_wires = 0, out_wires = 0;
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//for (auto &si : signal_list)
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// if (si.is_port) {
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// char buffer[100];
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// snprintf(buffer, 100, "\\n%d", si.id);
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// RTLIL::SigSig conn;
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// if (si.type != G(NONE)) {
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// conn.first = si.bit;
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// conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
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// out_wires++;
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// } else {
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// conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
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// conn.second = si.bit;
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// in_wires++;
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// }
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// module->connect(conn);
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// }
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// Stitch in mapped_mod's inputs/outputs into module
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for (auto &it : mapped_mod->wires_) {
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