mirror of https://github.com/YosysHQ/yosys.git
Fix issue where keep signal became PI, but also box was adding CI driver
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a41553a861
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887c31f33b
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@ -392,6 +392,12 @@ struct XAigerWriter
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if (O != b)
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alias_map[O] = b;
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undriven_bits.erase(O);
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auto jt = input_bits.find(b);
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if (jt != input_bits.end()) {
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log_assert(b.wire->attributes.count("\\keep"));
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input_bits.erase(b);
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}
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}
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}
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}
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@ -409,9 +415,10 @@ struct XAigerWriter
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if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
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|| wire->attributes.count("\\keep")) {
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log_assert(input_bits.count(bit) && output_bits.count(bit));
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RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
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RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
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RTLIL::Wire *new_wire = module->wire(wire_name);
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if (!new_wire)
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new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire));
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new_wire = module->addWire(wire_name, GetSize(wire));
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SigBit new_bit(new_wire, bit.offset);
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module->connect(new_bit, bit);
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if (not_map.count(bit))
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@ -468,12 +475,15 @@ struct XAigerWriter
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for (auto bit : input_bits) {
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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}
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for (auto &c : ci_bits) {
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RTLIL::SigBit bit = std::get<0>(c);
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aig_m++, aig_i++;
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aig_map[std::get<0>(c)] = 2*aig_m;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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}
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if (imode && input_bits.empty()) {
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@ -538,8 +548,7 @@ struct XAigerWriter
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for (auto &c : co_bits) {
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RTLIL::SigBit bit = std::get<0>(c);
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std::get<4>(c) = aig_o++;
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ordered_outputs[bit] = std::get<4>(c);
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std::get<4>(c) = ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back(bit2aig(bit));
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}
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@ -720,10 +729,15 @@ struct XAigerWriter
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if (omode && num_outputs == 0)
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num_outputs = 1;
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write_h_buffer(1);
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log_debug("ciNum = %zu\n", input_bits.size() + ci_bits.size());
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write_h_buffer(input_bits.size() + ci_bits.size());
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log_debug("coNum = %zu\n", num_outputs + co_bits.size());
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write_h_buffer(num_outputs + co_bits.size());
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log_debug("piNum = %zu\n", input_bits.size());
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write_h_buffer(input_bits.size());
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log_debug("poNum = %d\n", num_outputs);
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write_h_buffer(num_outputs);
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log_debug("boxNum = %zu\n", box_list.size());
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write_h_buffer(box_list.size());
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RTLIL::Module *holes_module = nullptr;
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