mirror of https://github.com/YosysHQ/yosys.git
read_xaiger() to name box signals
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4a6b9af227
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@ -689,23 +689,27 @@ void AigerReader::post_process()
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RTLIL::Wire* w = box_module->wire(port_name);
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log_assert(w);
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RTLIL::SigSpec rhs;
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RTLIL::Wire* wire = nullptr;
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for (int i = 0; i < GetSize(w); i++) {
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if (w->port_input) {
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log_assert(static_cast<unsigned>(co_count) < outputs.size());
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RTLIL::Wire* wire = outputs[co_count++];
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wire = outputs[co_count++];
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log_assert(wire);
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log_assert(wire->port_output);
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wire->port_output = false;
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rhs.append(wire);
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}
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if (w->port_output) {
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log_assert(static_cast<unsigned>(pi_count + ci_count) < inputs.size());
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RTLIL::Wire* wire = inputs[pi_count + ci_count++];
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wire = inputs[pi_count + ci_count++];
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log_assert(wire);
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log_assert(wire->port_input);
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wire->port_input = false;
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rhs.append(wire);
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}
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rhs.append(wire);
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if (GetSize(w) == 1)
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module->rename(wire, RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name))));
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else
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module->rename(wire, RTLIL::escape_id(stringf("%s.%s[%d]", log_id(cell), log_id(port_name), i)));
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}
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cell->setPort(port_name, rhs);
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}
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