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read_xaiger() to name box signals

This commit is contained in:
Eddie Hung 2019-05-30 16:02:40 -07:00
parent 4a6b9af227
commit a41553a861
1 changed files with 8 additions and 4 deletions
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12
frontends/aiger/aigerparse.cc
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@ -689,23 +689,27 @@ void AigerReader::post_process()
RTLIL::Wire* w = box_module->wire(port_name);
log_assert(w);
RTLIL::SigSpec rhs;
RTLIL::Wire* wire = nullptr;
for (int i = 0; i < GetSize(w); i++) {
if (w->port_input) {
log_assert(static_cast<unsigned>(co_count) < outputs.size());
RTLIL::Wire* wire = outputs[co_count++];
wire = outputs[co_count++];
log_assert(wire);
log_assert(wire->port_output);
wire->port_output = false;
rhs.append(wire);
}
if (w->port_output) {
log_assert(static_cast<unsigned>(pi_count + ci_count) < inputs.size());
RTLIL::Wire* wire = inputs[pi_count + ci_count++];
wire = inputs[pi_count + ci_count++];
log_assert(wire);
log_assert(wire->port_input);
wire->port_input = false;
rhs.append(wire);
}
rhs.append(wire);
if (GetSize(w) == 1)
module->rename(wire, RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name))));
else
module->rename(wire, RTLIL::escape_id(stringf("%s.%s[%d]", log_id(cell), log_id(port_name), i)));
}
cell->setPort(port_name, rhs);
}