mirror of https://github.com/YosysHQ/yosys.git
Minor correction
Minor typo error correction in -expose with setundef
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@ -89,7 +89,6 @@ static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std:
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return wire;
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}
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struct SetundefWorker
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{
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int next_bit_mode;
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@ -304,7 +303,7 @@ struct SetundefPass : public Pass {
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else {
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string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
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wire = add_wire(design, module, name, c.width, true, false, false);
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module->connect(RTLIL::SigSig(c.wire, wire));
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module->connect(RTLIL::SigSig(c, wire));
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}
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log("Exposing undriven wire %s as input.\n", wire->name.c_str());
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}
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