mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'eddie/fix_retime' into xc7srl
This commit is contained in:
commit
4afcad70e2
|
@ -1728,7 +1728,7 @@ struct AbcPass : public Pass {
|
|||
signal_init[initsig[i]] = State::S0;
|
||||
break;
|
||||
case State::S1:
|
||||
signal_init[initsig[i]] = State::S0;
|
||||
signal_init[initsig[i]] = State::S1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
|
@ -0,0 +1,6 @@
|
|||
module retime_test(input clk, input [7:0] a, output z);
|
||||
reg [7:0] ff = 8'hF5;
|
||||
always @(posedge clk)
|
||||
ff <= {ff[6:0], ^a};
|
||||
assign z = ff[7];
|
||||
endmodule
|
Loading…
Reference in New Issue