mirror of https://github.com/YosysHQ/yosys.git
Add retime test
This commit is contained in:
parent
d559023007
commit
ad602438b8
|
@ -0,0 +1,6 @@
|
|||
module retime_test(input clk, input [7:0] a, output z);
|
||||
reg [7:0] ff = 8'hF5;
|
||||
always @(posedge clk)
|
||||
ff <= {ff[6:0], ^a};
|
||||
assign z = ff[7];
|
||||
endmodule
|
Loading…
Reference in New Issue