mirror of https://github.com/YosysHQ/yosys.git
Added "extract" pass (not functional yet)
This commit is contained in:
Clifford Wolf
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99d73fe028
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OBJS += passes/extract/extract.o
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "libs/subcircuit/subcircuit.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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namespace
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{
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struct bit_ref_t {
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std::string cell, port;
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int bit;
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};
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bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, RTLIL::Design *sel = NULL)
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{
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SigMap sigmap(mod);
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std::map<RTLIL::SigChunk, bit_ref_t> sig_bit_ref;
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if (sel && !sel->selected(mod)) {
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log(" Skipping module %s as it is not selected.\n", mod->name.c_str());
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return false;
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}
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if (mod->memories.size() > 0 || mod->processes.size() > 0) {
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log(" Skipping module %s as it contains unprocessed memories or processes.\n", mod->name.c_str());
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return false;
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}
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for (auto &cell_it : mod->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (sel && !sel->selected(mod, cell))
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continue;
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std::string type = cell->type;
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if (sel == NULL && type.substr(0, 2) == "\\$")
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type = type.substr(1);
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graph.createNode(cell->name, type, (void*)cell);
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for (auto &conn : cell->connections)
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{
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RTLIL::SigSpec conn_sig = conn.second;
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sigmap.apply(conn_sig);
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conn_sig.expand();
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graph.createPort(cell->name, conn.first, conn.second.width);
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for (size_t i = 0; i < conn_sig.chunks.size(); i++)
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{
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auto &chunk = conn_sig.chunks[i];
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assert(chunk.width == 1);
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if (sig_bit_ref.count(chunk) == 0) {
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bit_ref_t &bit_ref = sig_bit_ref[chunk];
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bit_ref.cell = cell->name;
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bit_ref.port = conn.first;
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bit_ref.bit = i;
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}
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bit_ref_t &bit_ref = sig_bit_ref[chunk];
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graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i);
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}
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}
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}
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for (auto &cell_it : mod->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (sel && !sel->selected(mod, cell))
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for (auto &conn : cell->connections)
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{
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RTLIL::SigSpec conn_sig = conn.second;
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sigmap.apply(conn_sig);
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conn_sig.expand();
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for (auto &chunk : conn_sig.chunks)
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if (sig_bit_ref.count(chunk) != 0) {
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bit_ref_t &bit_ref = sig_bit_ref[chunk];
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graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
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}
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}
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}
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for (auto &wire_it : mod->wires)
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{
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RTLIL::Wire *wire = wire_it.second;
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if (wire->port_id > 0)
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{
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RTLIL::SigSpec conn_sig(wire);
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sigmap.apply(conn_sig);
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conn_sig.expand();
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for (auto &chunk : conn_sig.chunks)
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if (sig_bit_ref.count(chunk) != 0) {
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bit_ref_t &bit_ref = sig_bit_ref[chunk];
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graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
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}
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}
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}
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return true;
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}
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}
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struct ExtractPass : public Pass {
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ExtractPass() : Pass("extract") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing EXTRACT pass (map subcircuits to cells).\n");
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log_push();
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std::string filename;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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filename = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (filename.empty())
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log_cmd_error("Missing option -map <verilog_file>.\n");
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RTLIL::Design *map = new RTLIL::Design;
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FILE *f = fopen(filename.c_str(), "rt");
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if (f == NULL)
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log_error("Can't open map file `%s'\n", filename.c_str());
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Frontend::frontend_call(map, f, filename, "verilog");
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fclose(f);
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SubCircuit::Solver solver;
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std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
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log_header("Creating graphs for SubCircuit library.\n");
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for (auto &mod_it : map->modules) {
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SubCircuit::Graph mod_graph;
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std::string graph_name = "needle_" + mod_it.first.substr(mod_it.first[0] == '\\' ? 1 : 0);
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log("Creating needle graph %s.\n", graph_name.c_str());
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if (module2graph(mod_graph, mod_it.second)) {
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solver.addGraph(graph_name, mod_graph);
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needle_map[graph_name] = mod_it.second;
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}
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}
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for (auto &mod_it : design->modules) {
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SubCircuit::Graph mod_graph;
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std::string graph_name = "haystack_" + mod_it.first.substr(mod_it.first[0] == '\\' ? 1 : 0);
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log("Creating haystack graph %s.\n", graph_name.c_str());
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if (module2graph(mod_graph, mod_it.second, design)) {
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solver.addGraph(graph_name, mod_graph);
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haystack_map[graph_name] = mod_it.second;
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}
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}
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log_header("Running solver from SubCircuit library.\n");
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solver.setVerbose();
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std::vector<SubCircuit::Solver::Result> results;
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for (auto &needle_it : needle_map)
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for (auto &haystack_it : haystack_map) {
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log("Solving for %s in %s.\n", needle_it.first.c_str(), haystack_it.first.c_str());
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solver.solve(results, needle_it.first, haystack_it.first, false);
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}
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for (int i = 0; i < int(results.size()); i++) {
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log("\nMatch #%d: (%s in %s)\n", i, results[i].needleGraphId.c_str(), results[i].haystackGraphId.c_str());
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for (const auto & it : results[i].mappings) {
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log(" %s -> %s", it.first.c_str(), it.second.haystackNodeId.c_str());
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for (const auto & it2 : it.second.portMapping)
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log(" %s:%s", it2.first.c_str(), it2.second.c_str());
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log("\n");
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}
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}
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delete map;
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log_pop();
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log("\n** UNFINISHED IMPLEMENTATION **\n");
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log_cmd_error("TBD: Replace found subcircuits with cells.\n");
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}
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} ExtractPass;
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