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Minor fixes in abc build instructions and abc pass

This commit is contained in:
Clifford Wolf 2013-08-20 09:46:05 +02:00
parent 0003743432
commit 1af1cebb64
2 changed files with 5 additions and 5 deletions
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2
Makefile
View File

@ -86,7 +86,7 @@ yosys-svgviewer: libs/svgviewer/*.h libs/svgviewer/*.cpp
abc:
test -d abc || hg clone https://bitbucket.org/alanmi/abc abc
cd abc && hg pull && make
cd abc && hg pull && hg update && make
cp abc/abc yosys-abc
test: yosys

8
passes/abc/abc.cc
View File

@ -457,21 +457,21 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
int buffer_pos = 0;
if (!liberty_file.empty())
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
"%s -c 'read_verilog %s/input.v; read_liberty %s; map; ",
"%s -s -c 'read_verilog %s/input.v; read_liberty %s; map; ",
exe_file.c_str(), tempdir_name, liberty_file.c_str());
else
if (!script_file.empty())
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
"%s -c 'read_verilog %s/input.v; source %s; ",
"%s -s -c 'read_verilog %s/input.v; source %s; ",
exe_file.c_str(), tempdir_name, script_file.c_str());
else
if (lut_mode)
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
"%s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ",
"%s -s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ",
exe_file.c_str(), tempdir_name, tempdir_name);
else
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
"%s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ",
"%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ",
exe_file.c_str(), tempdir_name, tempdir_name);
if (lut_mode)
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name);