mirror of https://github.com/YosysHQ/yosys.git
Fixed width and sign detection for ** operator
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8656b1c08f
commit
0003743432
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@ -567,6 +567,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
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case AST_SHIFT_RIGHT:
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case AST_SHIFT_SLEFT:
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case AST_SHIFT_SRIGHT:
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case AST_POW:
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children[0]->detectSignWidthWorker(width_hint, sign_hint);
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break;
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@ -585,7 +586,6 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
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case AST_MUL:
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case AST_DIV:
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case AST_MOD:
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case AST_POW:
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for (auto child : children)
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child->detectSignWidthWorker(width_hint, sign_hint);
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break;
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@ -963,8 +963,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (width_hint < 0)
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detectSignWidth(width_hint, sign_hint);
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RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
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RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
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int width = std::max(left.width, right.width);
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RTLIL::SigSpec right = type == AST_POW ? children[1]->genRTLIL() : children[1]->genRTLIL(width_hint, sign_hint);
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int width = type == AST_POW ? left.width : std::max(left.width, right.width);
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if (width > width_hint && width_hint > 0)
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width = width_hint;
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if (width < width_hint) {
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