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Removed $bu0 cell type

This commit is contained in:
Clifford Wolf 2014-09-04 02:07:52 +02:00
parent b9cb483f3e
commit 8927aa6148
18 changed files with 27 additions and 103 deletions
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1
backends/verilog/verilog_backend.cc
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@ -538,7 +538,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
HANDLE_UNIOP("$not", "~")
HANDLE_UNIOP("$pos", "+")
HANDLE_UNIOP("$bu0", "+")
HANDLE_UNIOP("$neg", "-")
HANDLE_BINOP("$and", "&")

10
frontends/ast/genrtlil.cc
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@ -70,7 +70,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
}
// helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed, std::string celltype)
static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
{
if (width <= sig.size()) {
sig.extend(width, is_signed);
@ -80,7 +80,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
std::stringstream sstr;
sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
@ -1012,7 +1012,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = arg.size();
if (width_hint > 0) {
width = width_hint;
widthExtend(this, arg, width, is_signed, "$pos");
widthExtend(this, arg, width, is_signed);
}
return uniop2rtlil(this, type_name, width, arg);
}
@ -1167,8 +1167,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = std::max(val1.size(), val2.size());
is_signed = children[1]->is_signed && children[2]->is_signed;
widthExtend(this, val1, width, is_signed, "$bu0");
widthExtend(this, val2, width, is_signed, "$bu0");
widthExtend(this, val1, width, is_signed);
widthExtend(this, val2, width, is_signed);
RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);

21
kernel/calc.cc
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@ -26,19 +26,6 @@
YOSYS_NAMESPACE_BEGIN
static void extend(RTLIL::Const &arg, int width, bool is_signed)
{
RTLIL::State padding = RTLIL::State::S0;
if (arg.bits.size() > 0 && (is_signed || arg.bits.back() > RTLIL::State::S1))
padding = arg.bits.back();
while (int(arg.bits.size()) < width)
arg.bits.push_back(padding);
arg.bits.resize(width);
}
static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
{
RTLIL::State padding = RTLIL::State::S0;
@ -580,14 +567,6 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo
return arg1_ext;
}
RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
extend_u0(arg1_ext, result_len, signed1);
return arg1_ext;
}
RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;

5
kernel/celltypes.h
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@ -86,7 +86,7 @@ struct CellTypes
void setup_internals()
{
std::vector<RTLIL::IdString> unary_ops = {
"$not", "$pos", "$bu0", "$neg",
"$not", "$pos", "$neg",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$logic_not", "$slice", "$lut"
};
@ -219,7 +219,7 @@ struct CellTypes
type = "$shl";
if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && type != "$shift" && type != "$shiftx" &&
type != "$pos" && type != "$neg" && type != "$not" && type != "$bu0") {
type != "$pos" && type != "$neg" && type != "$not") {
if (!signed1 || !signed2)
signed1 = false, signed2 = false;
}
@ -259,7 +259,6 @@ struct CellTypes
HANDLE_CELL_TYPE(mod)
HANDLE_CELL_TYPE(pow)
HANDLE_CELL_TYPE(pos)
HANDLE_CELL_TYPE(bu0)
HANDLE_CELL_TYPE(neg)
#undef HANDLE_CELL_TYPE

3
kernel/rtlil.cc
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@ -563,7 +563,7 @@ namespace {
cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
return;
if (cell->type.in("$not", "$pos", "$bu0", "$neg")) {
if (cell->type.in("$not", "$pos", "$neg")) {
param_bool("\\A_SIGNED");
port("\\A", param("\\A_WIDTH"));
port("\\Y", param("\\Y_WIDTH"));
@ -1326,7 +1326,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
}
DEF_METHOD(Not, sig_a.size(), "$not")
DEF_METHOD(Pos, sig_a.size(), "$pos")
DEF_METHOD(Bu0, sig_a.size(), "$bu0")
DEF_METHOD(Neg, sig_a.size(), "$neg")
DEF_METHOD(ReduceAnd, 1, "$reduce_and")
DEF_METHOD(ReduceOr, 1, "$reduce_or")

2
kernel/rtlil.h
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@ -314,7 +314,6 @@ namespace RTLIL
RTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_bu0 (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
@ -651,7 +650,6 @@ public:
RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addBu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);

6
kernel/satgen.h
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@ -451,7 +451,7 @@ struct SatGen
return true;
}
if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg")
if (cell->type == "$pos" || cell->type == "$neg")
{
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
@ -459,7 +459,7 @@ struct SatGen
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (cell->type == "$pos" || cell->type == "$bu0") {
if (cell->type == "$pos") {
ez->assume(ez->vec_eq(a, yy));
} else {
std::vector<int> zero(a.size(), ez->FALSE);
@ -472,7 +472,7 @@ struct SatGen
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell);
if (cell->type == "$pos" || cell->type == "$bu0") {
if (cell->type == "$pos") {
ez->assume(ez->vec_eq(undef_a, undef_y));
} else {
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);

6
manual/CHAPTER_CellLib.tex
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@ -97,12 +97,6 @@ The width of the output port \B{Y}.
Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always
extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments
with {\tt x}-bits if the most significant bit is {\tt x}.) This is used
internally to correctly implement the {\tt ==} and {\tt !=} operators for
constant arguments.
\subsection{Multiplexers}
Multiplexers are generated by the Verilog HDL frontend for {\tt

2
manual/PRESENTATION_Prog.tex
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@ -300,7 +300,7 @@ The {\tt type} may refer to another module in the same design, a cell name from
cell name from the internal cell library:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
$not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
$not $pos $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
$reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
$pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_

2
manual/command-reference-manual.tex
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@ -1204,7 +1204,7 @@ unless another prefix is specified using -prefix <prefix>.
This pass maps a small selection of simple coarse-grain cells to yosys gate
primitives. The following internal cell types are mapped by this pass:
$not, $pos, $bu0, $and, $or, $xor, $xnor
$not, $pos, $and, $or, $xor, $xnor
$reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
$logic_not, $logic_and, $logic_or, $mux
$sr, $dff, $dffsr, $adff, $dlatch

2
passes/cmds/stat.cc
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@ -99,7 +99,7 @@ namespace
if (width_mode)
{
if (cell_type.in("$not", "$pos", "$bu0", "$neg",
if (cell_type.in("$not", "$pos", "$neg",
"$logic_not", "$logic_and", "$logic_or",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$lut", "$and", "$or", "$xor", "$xnor",

10
passes/opt/opt_const.cc
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@ -181,7 +181,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
log("\n");
}
cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str());
cover_list("opt.opt_const.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
module->remove(cell);
did_something = true;
@ -236,7 +236,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (do_fine)
{
if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" ||
if (cell->type == "$not" || cell->type == "$pos" ||
cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")
if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map))
goto next_cell;
@ -586,7 +586,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (!keepdc)
{
bool identity_bu0 = false;
bool identity_wrt_a = false;
bool identity_wrt_b = false;
@ -607,7 +606,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
if (b.is_fully_const() && b.as_bool() == false)
identity_wrt_a = true, identity_bu0 = true;
identity_wrt_a = true;
}
if (cell->type == "$mul")
@ -646,7 +645,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
}
cell->type = identity_bu0 ? "$bu0" : "$pos";
cell->type = "$pos";
cell->unsetPort("\\B");
cell->parameters.erase("\\B_WIDTH");
cell->parameters.erase("\\B_SIGNED");
@ -840,7 +839,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
FOLD_2ARG_CELL(pow)
FOLD_1ARG_CELL(pos)
FOLD_1ARG_CELL(bu0)
FOLD_1ARG_CELL(neg)
// be very conservative with optimizing $mux cells as we do not want to break mux trees

1
passes/opt/share.cc
View File

@ -923,7 +923,6 @@ struct SharePass : public Pass {
config.generic_uni_ops.insert("$not");
// config.generic_uni_ops.insert("$pos");
// config.generic_uni_ops.insert("$bu0");
config.generic_uni_ops.insert("$neg");
config.generic_cbin_ops.insert("$and");

6
passes/opt/wreduce.cc
View File

@ -37,7 +37,7 @@ struct WreduceConfig
WreduceConfig()
{
supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg";
supported_cell_types << "$not" << "$pos" << "$neg";
supported_cell_types << "$and" << "$or" << "$xor" << "$xnor";
supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx";
supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt";
@ -181,7 +181,7 @@ struct WreduceWorker
int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1;
int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1;
if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y")));
max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y")));
}
@ -216,7 +216,7 @@ struct WreduceWorker
}
}
if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor"))
if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor"))
{
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();

13
passes/techmap/simplemap.cc
View File

@ -45,16 +45,6 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
}
static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
@ -386,7 +376,6 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
{
mappers["$not"] = simplemap_not;
mappers["$pos"] = simplemap_pos;
mappers["$bu0"] = simplemap_bu0;
mappers["$and"] = simplemap_bitop;
mappers["$or"] = simplemap_bitop;
mappers["$xor"] = simplemap_bitop;
@ -420,7 +409,7 @@ struct SimplemapPass : public Pass {
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
log("primitives. The following internal cell types are mapped by this pass:\n");
log("\n");
log(" $not, $pos, $bu0, $and, $or, $xor, $xnor\n");
log(" $not, $pos, $and, $or, $xor, $xnor\n");
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
log(" $logic_not, $logic_and, $logic_or, $mux\n");
log(" $sr, $dff, $dffsr, $adff, $dlatch\n");

1
passes/tests/test_cell.cc
View File

@ -441,7 +441,6 @@ struct TestCellPass : public Pass {
cell_types["$not"] = "ASY";
cell_types["$pos"] = "ASY";
cell_types["$bu0"] = "ASY";
cell_types["$neg"] = "ASY";
cell_types["$and"] = "ABSY";

24
techlibs/common/simlib.v
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@ -53,30 +53,6 @@ endgenerate
endmodule
// --------------------------------------------------------
module \$bu0 (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1
assign Y[A_WIDTH-1:0] = A;
assign Y[Y_WIDTH-1:A_WIDTH] = 0;
end else if (A_SIGNED) begin:BLOCK2
assign Y = $signed(A);
end else begin:BLOCK3
assign Y = A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$pos (A, Y);

15
techlibs/common/techmap.v
View File

@ -38,11 +38,6 @@
// Use simplemap for trivial cell types
// --------------------------------------------------------
(* techmap_simplemap *)
(* techmap_celltype = "$pos $bu0" *)
module simplemap_buffers;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$not $and $or $xor $xnor" *)
module simplemap_bool_ops;
@ -59,7 +54,7 @@ module simplemap_logic_ops;
endmodule
(* techmap_simplemap *)
(* techmap_celltype = "$slice $concat $mux" *)
(* techmap_celltype = "$pos $slice $concat $mux" *)
module simplemap_various;
endmodule
@ -738,8 +733,8 @@ module \$eq (A, B, Y);
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = ~|(A_buf ^ B_buf);
endmodule
@ -759,8 +754,8 @@ module \$ne (A, B, Y);
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = |(A_buf ^ B_buf);
endmodule