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Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
memory_bram: Fix initdata bit order after shuffling
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a2154c1be0
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@ -472,8 +472,12 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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std::vector<SigSpec> new_wr_en(GetSize(old_wr_en));
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std::vector<SigSpec> new_wr_data(GetSize(old_wr_data));
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std::vector<SigSpec> new_rd_data(GetSize(old_rd_data));
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std::vector<std::vector<State>> new_initdata;
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std::vector<int> shuffle_map;
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if (cell_init)
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new_initdata.resize(mem_size);
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for (auto &it : en_order)
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{
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auto &bits = bits_wr_en.at(it);
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@ -489,6 +493,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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}
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for (int j = 0; j < rd_ports; j++)
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new_rd_data[j].append(old_rd_data[j][bits[i]]);
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if (cell_init) {
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for (int j = 0; j < mem_size; j++)
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new_initdata[j].push_back(initdata[j][bits[i]]);
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}
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shuffle_map.push_back(bits[i]);
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}
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@ -499,6 +507,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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}
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for (int j = 0; j < rd_ports; j++)
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new_rd_data[j].append(State::Sx);
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if (cell_init) {
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for (int j = 0; j < mem_size; j++)
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new_initdata[j].push_back(State::Sx);
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}
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shuffle_map.push_back(-1);
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}
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}
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@ -522,6 +534,11 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
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for (int i = 0; i < rd_ports; i++)
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rd_data.replace(i*mem_width, new_rd_data[i]);
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if (cell_init) {
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for (int i = 0; i < mem_size; i++)
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initdata[i] = Const(new_initdata[i]);
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}
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}
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// assign write ports
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