mirror of https://github.com/YosysHQ/yosys.git
Removed CHECK() macro from libparse.cc (was using non-std c features)
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09d2e5cf5d
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@ -244,21 +244,6 @@ void LibertyParser::error()
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/**** BEGIN: http://svn.clifford.at/tools/trunk/examples/check.h ****/
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// This is to not confuse the VIM syntax highlighting
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#define CHECK_VAL_OPEN (
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#define CHECK_VAL_CLOSE )
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#define CHECK(result, check) \
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CHECK_VAL_OPEN{ \
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auto _R = (result); \
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if (!(_R check)) { \
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fprintf(stderr, "Error from '%s' (%ld %s) in %s:%d.\n", \
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#result, (long int)_R, #check, __FILE__, __LINE__); \
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abort(); \
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} \
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_R; \
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}CHECK_VAL_CLOSE
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#define CHECK_NV(result, check) \
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do { \
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auto _R = (result); \
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@ -280,6 +265,14 @@ void LibertyParser::error()
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/**** END: http://svn.clifford.at/tools/trunk/examples/check.h ****/
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LibertyAst *find_non_null(LibertyAst *node, const char *name)
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{
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LibertyAst *ret = node->find(name);
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if (ret == NULL)
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fprintf(stderr, "Error: expected to find `%s' node.\n", name);
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return ret;
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}
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std::string func2vl(std::string str)
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{
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for (size_t pos = str.find_first_of("\" \t"); pos != std::string::npos; pos = str.find_first_of("\" \t")) {
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@ -388,7 +381,7 @@ void gen_verilogsim_cell(LibertyAst *ast)
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if (child->id != "pin")
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continue;
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CHECK_NV(child->args.size(), == 1);
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LibertyAst *dir = CHECK(child->find("direction"), != NULL);
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LibertyAst *dir = find_non_null(child, "direction");
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LibertyAst *func = child->find("function");
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printf(" %s %s;\n", dir->value.c_str(), child->args[0].c_str());
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if (func != NULL)
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@ -428,8 +421,8 @@ void gen_verilogsim_cell(LibertyAst *ast)
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const char *else_prefix = "";
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if (!clear_expr.empty() && !preset_expr.empty()) {
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printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear_expr.c_str(), preset_expr.c_str());
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clear_preset_var(iq_var, CHECK(child->find("clear_preset_var1"), != NULL)->value);
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clear_preset_var(iqn_var, CHECK(child->find("clear_preset_var2"), != NULL)->value);
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clear_preset_var(iq_var, find_non_null(child, "clear_preset_var1")->value);
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clear_preset_var(iqn_var, find_non_null(child, "clear_preset_var2")->value);
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printf(" end\n");
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else_prefix = "else ";
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}
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@ -449,7 +442,7 @@ void gen_verilogsim_cell(LibertyAst *ast)
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}
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if (*else_prefix)
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printf(" %sbegin\n", else_prefix);
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std::string expr = CHECK(child->find("next_state"), != NULL)->value;
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std::string expr = find_non_null(child, "next_state")->value;
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printf(" // %s\n", expr.c_str());
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printf(" %s <= %s;\n", iq_var.c_str(), func2vl(expr).c_str());
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printf(" %s <= ~(%s);\n", iqn_var.c_str(), func2vl(expr).c_str());
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@ -481,8 +474,8 @@ void gen_verilogsim_cell(LibertyAst *ast)
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const char *else_prefix = "";
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if (!clear_expr.empty() && !preset_expr.empty()) {
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printf(" %sif ((%s) && (%s)) begin\n", else_prefix, clear_expr.c_str(), preset_expr.c_str());
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clear_preset_var(iq_var, CHECK(child->find("clear_preset_var1"), != NULL)->value);
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clear_preset_var(iqn_var, CHECK(child->find("clear_preset_var2"), != NULL)->value);
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clear_preset_var(iq_var, find_non_null(child, "clear_preset_var1")->value);
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clear_preset_var(iqn_var, find_non_null(child, "clear_preset_var2")->value);
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printf(" end\n");
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else_prefix = "else ";
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}
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@ -502,7 +495,7 @@ void gen_verilogsim_cell(LibertyAst *ast)
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}
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if (!enable_expr.empty()) {
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printf(" %sif (%s) begin\n", else_prefix, enable_expr.c_str());
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std::string expr = CHECK(child->find("data_in"), != NULL)->value;
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std::string expr = find_non_null(child, "data_in")->value;
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printf(" %s <= %s;\n", iq_var.c_str(), func2vl(expr).c_str());
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printf(" %s <= ~(%s);\n", iqn_var.c_str(), func2vl(expr).c_str());
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printf(" end\n");
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