mirror of https://github.com/YosysHQ/yosys.git
Fixed test_autotb for modules with many cell ports
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93e107e455
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958fb29c76
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@ -218,7 +218,8 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter)
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if (len > 0)
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header2 += shorthand, len--;
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header1.push_back(" " + it->first);
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header1.back()[0] = shorthand++;
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header1.back()[0] = shorthand;
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shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
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}
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else {
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f << stringf(" 1'bx");
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@ -237,7 +238,8 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter)
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if (len > 0)
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header2 += shorthand, len--;
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header1.push_back(" " + it->first);
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header1.back()[0] = shorthand++;
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header1.back()[0] = shorthand;
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shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
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}
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} else {
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f << stringf(" 1'bx");
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@ -256,7 +258,8 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter)
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if (len > 0)
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header2 += shorthand, len--;
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header1.push_back(" " + it->first);
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header1.back()[0] = shorthand++;
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header1.back()[0] = shorthand;
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shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
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}
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} else {
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f << stringf(" 1'bx");
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