mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
Add pmux2shiftx command
This commit is contained in:
Clifford Wolf
GitHub
commit
a98b171814
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@ -13,5 +13,6 @@ OBJS += passes/opt/wreduce.o
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OBJS += passes/opt/opt_demorgan.o
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OBJS += passes/opt/rmports.o
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OBJS += passes/opt/opt_lut.o
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OBJS += passes/opt/pmux2shiftx.o
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endif
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@ -0,0 +1,831 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OnehotDatabase
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{
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Module *module;
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const SigMap &sigmap;
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bool verbose = false;
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bool initialized = false;
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pool<SigBit> init_ones;
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dict<SigSpec, pool<SigSpec>> sig_sources_db;
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dict<SigSpec, bool> sig_onehot_cache;
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pool<SigSpec> recursion_guard;
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OnehotDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
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{
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}
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void initialize()
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{
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log_assert(!initialized);
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initialized = true;
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for (auto wire : module->wires())
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{
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auto it = wire->attributes.find("\\init");
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if (it == wire->attributes.end())
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continue;
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auto &val = it->second;
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int width = std::max(GetSize(wire), GetSize(val));
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for (int i = 0; i < width; i++)
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if (val[i] == State::S1)
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init_ones.insert(sigmap(SigBit(wire, i)));
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}
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for (auto cell : module->cells())
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{
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vector<SigSpec> inputs;
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SigSpec output;
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if (cell->type.in("$adff", "$dff", "$dffe", "$dlatch", "$ff"))
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{
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output = cell->getPort("\\Q");
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if (cell->type == "$adff")
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inputs.push_back(cell->getParam("\\ARST_VALUE"));
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inputs.push_back(cell->getPort("\\D"));
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}
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if (cell->type.in("$mux", "$pmux"))
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{
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output = cell->getPort("\\Y");
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inputs.push_back(cell->getPort("\\A"));
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SigSpec B = cell->getPort("\\B");
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for (int i = 0; i < GetSize(B); i += GetSize(output))
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inputs.push_back(B.extract(i, GetSize(output)));
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}
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if (!output.empty())
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{
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output = sigmap(output);
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auto &srcs = sig_sources_db[output];
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for (auto src : inputs) {
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while (!src.empty() && src[GetSize(src)-1] == State::S0)
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src.remove(GetSize(src)-1);
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srcs.insert(sigmap(src));
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}
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}
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}
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}
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void query_worker(const SigSpec &sig, bool &retval, bool &cache, int indent)
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{
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if (verbose)
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log("%*s %s\n", indent, "", log_signal(sig));
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log_assert(retval);
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if (recursion_guard.count(sig)) {
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if (verbose)
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log("%*s - recursion\n", indent, "");
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cache = false;
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return;
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}
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auto it = sig_onehot_cache.find(sig);
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if (it != sig_onehot_cache.end()) {
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if (verbose)
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log("%*s - cached (%s)\n", indent, "", it->second ? "true" : "false");
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if (!it->second)
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retval = false;
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return;
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}
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bool found_init_ones = false;
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for (auto bit : sig) {
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if (init_ones.count(bit)) {
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if (found_init_ones) {
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if (verbose)
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log("%*s - non-onehot init value\n", indent, "");
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retval = false;
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break;
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}
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found_init_ones = true;
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}
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}
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if (retval)
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{
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if (sig.is_fully_const())
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{
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bool found_ones = false;
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for (auto bit : sig) {
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if (bit == State::S1) {
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if (found_ones) {
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if (verbose)
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log("%*s - non-onehot constant\n", indent, "");
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retval = false;
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break;
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}
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found_ones = true;
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}
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}
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}
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else
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{
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auto srcs = sig_sources_db.find(sig);
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if (srcs == sig_sources_db.end()) {
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if (verbose)
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log("%*s - no sources for non-const signal\n", indent, "");
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retval = false;
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} else {
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for (auto &src : srcs->second) {
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bool child_cache = true;
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recursion_guard.insert(sig);
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query_worker(src, retval, child_cache, indent+4);
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recursion_guard.erase(sig);
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if (!child_cache)
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cache = false;
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if (!retval)
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break;
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}
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}
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}
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}
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// it is always safe to cache a negative result
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if (cache || !retval)
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sig_onehot_cache[sig] = retval;
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}
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bool query(const SigSpec &sig)
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{
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bool retval = true;
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bool cache = true;
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if (verbose)
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log("** ONEHOT QUERY START (%s)\n", log_signal(sig));
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if (!initialized)
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initialize();
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query_worker(sig, retval, cache, 3);
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if (verbose)
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log("** ONEHOT QUERY RESULT = %s\n", retval ? "true" : "false");
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// it is always safe to cache the root result of a query
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if (!cache)
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sig_onehot_cache[sig] = retval;
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return retval;
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}
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};
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struct Pmux2ShiftxPass : public Pass {
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Pmux2ShiftxPass() : Pass("pmux2shiftx", "transform $pmux cells to $shiftx cells") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" pmux2shiftx [options] [selection]\n");
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log("\n");
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log("This pass transforms $pmux cells to $shiftx cells.\n");
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log("\n");
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log(" -v, -vv\n");
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log(" verbose output\n");
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log("\n");
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log(" -min_density <percentage>\n");
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log(" specifies the minimum density for the shifter\n");
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log(" default: 50\n");
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log("\n");
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log(" -min_choices <int>\n");
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log(" specified the minimum number of choices for a control signal\n");
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log(" default: 3\n");
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log("\n");
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log(" -onehot ignore|pmux|shiftx\n");
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log(" select strategy for one-hot encoded control signals\n");
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log(" default: pmux\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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int min_density = 50;
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int min_choices = 3;
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bool allow_onehot = false;
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bool optimize_onehot = true;
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bool verbose = false;
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bool verbose_onehot = false;
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log_header(design, "Executing PMUX2SHIFTX pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-min_density" && argidx+1 < args.size()) {
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min_density = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-min_choices" && argidx+1 < args.size()) {
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min_choices = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-onehot" && argidx+1 < args.size() && args[argidx+1] == "ignore") {
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argidx++;
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allow_onehot = false;
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optimize_onehot = false;
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continue;
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}
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if (args[argidx] == "-onehot" && argidx+1 < args.size() && args[argidx+1] == "pmux") {
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argidx++;
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allow_onehot = false;
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optimize_onehot = true;
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continue;
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}
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if (args[argidx] == "-onehot" && argidx+1 < args.size() && args[argidx+1] == "shiftx") {
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argidx++;
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allow_onehot = true;
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optimize_onehot = false;
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continue;
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}
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if (args[argidx] == "-v") {
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verbose = true;
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continue;
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}
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if (args[argidx] == "-vv") {
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verbose = true;
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verbose_onehot = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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OnehotDatabase onehot_db(module, sigmap);
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onehot_db.verbose = verbose_onehot;
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dict<SigBit, pair<SigSpec, Const>> eqdb;
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for (auto cell : module->cells())
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{
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if (cell->type == "$eq")
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{
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dict<SigBit, State> bits;
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SigSpec A = sigmap(cell->getPort("\\A"));
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SigSpec B = sigmap(cell->getPort("\\B"));
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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if (a_width < b_width) {
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bool a_signed = cell->getParam("\\A_SIGNED").as_int();
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A.extend_u0(b_width, a_signed);
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}
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if (b_width < a_width) {
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bool b_signed = cell->getParam("\\B_SIGNED").as_int();
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B.extend_u0(a_width, b_signed);
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}
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for (int i = 0; i < GetSize(A); i++) {
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SigBit a_bit = A[i], b_bit = B[i];
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if (b_bit.wire && !a_bit.wire) {
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std::swap(a_bit, b_bit);
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}
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if (!a_bit.wire || b_bit.wire)
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goto next_cell;
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if (bits.count(a_bit))
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goto next_cell;
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bits[a_bit] = b_bit.data;
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}
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if (GetSize(bits) > 20)
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goto next_cell;
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bits.sort();
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pair<SigSpec, Const> entry;
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for (auto it : bits) {
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entry.first.append_bit(it.first);
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entry.second.bits.push_back(it.second);
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}
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eqdb[sigmap(cell->getPort("\\Y")[0])] = entry;
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goto next_cell;
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}
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if (cell->type == "$logic_not")
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{
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dict<SigBit, State> bits;
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SigSpec A = sigmap(cell->getPort("\\A"));
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for (int i = 0; i < GetSize(A); i++)
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bits[A[i]] = State::S0;
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bits.sort();
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pair<SigSpec, Const> entry;
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for (auto it : bits) {
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entry.first.append_bit(it.first);
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entry.second.bits.push_back(it.second);
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}
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eqdb[sigmap(cell->getPort("\\Y")[0])] = entry;
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goto next_cell;
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}
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next_cell:;
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}
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for (auto cell : module->selected_cells())
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{
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if (cell->type != "$pmux")
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continue;
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string src = cell->get_src_attribute();
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int width = cell->getParam("\\WIDTH").as_int();
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int width_bits = ceil_log2(width);
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int extwidth = width;
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while (extwidth & (extwidth-1))
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extwidth++;
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dict<SigSpec, pool<int>> seldb;
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SigSpec B = cell->getPort("\\B");
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SigSpec S = sigmap(cell->getPort("\\S"));
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for (int i = 0; i < GetSize(S); i++)
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{
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if (!eqdb.count(S[i]))
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continue;
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auto &entry = eqdb.at(S[i]);
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seldb[entry.first].insert(i);
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}
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if (seldb.empty())
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continue;
|
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bool printed_pmux_header = false;
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|
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if (verbose) {
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printed_pmux_header = true;
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log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
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log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
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}
|
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SigSpec updated_S = cell->getPort("\\S");
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SigSpec updated_B = cell->getPort("\\B");
|
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|
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while (!seldb.empty())
|
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{
|
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// pick the largest entry in seldb
|
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SigSpec sig = seldb.begin()->first;
|
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for (auto &it : seldb) {
|
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if (GetSize(sig) < GetSize(it.first))
|
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sig = it.first;
|
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else if (GetSize(seldb.at(sig)) < GetSize(it.second))
|
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sig = it.first;
|
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}
|
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|
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// find the relevant choices
|
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bool is_onehot = GetSize(sig) > 2;
|
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dict<Const, int> choices;
|
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for (int i : seldb.at(sig)) {
|
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Const val = eqdb.at(S[i]).second;
|
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int onebits = 0;
|
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for (auto b : val.bits)
|
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if (b == State::S1)
|
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onebits++;
|
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if (onebits > 1)
|
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is_onehot = false;
|
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choices[val] = i;
|
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}
|
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|
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// TBD: also find choices that are using signals that are subsets of the bits in "sig"
|
||||
|
||||
if (!verbose)
|
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{
|
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if (is_onehot && !allow_onehot && !optimize_onehot) {
|
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seldb.erase(sig);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (GetSize(choices) < min_choices) {
|
||||
seldb.erase(sig);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
if (!printed_pmux_header) {
|
||||
printed_pmux_header = true;
|
||||
log("Inspecting $pmux cell %s/%s.\n", log_id(module), log_id(cell));
|
||||
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
|
||||
}
|
||||
|
||||
log(" checking ctrl signal %s\n", log_signal(sig));
|
||||
|
||||
auto print_choices = [&]() {
|
||||
log(" table of choices:\n");
|
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for (auto &it : choices)
|
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log(" %3d: %s: %s\n", it.second, log_signal(it.first),
|
||||
log_signal(B.extract(it.second*width, width)));
|
||||
};
|
||||
|
||||
if (verbose)
|
||||
{
|
||||
if (is_onehot && !allow_onehot && !optimize_onehot) {
|
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print_choices();
|
||||
log(" ignoring one-hot encoding.\n");
|
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seldb.erase(sig);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (GetSize(choices) < min_choices) {
|
||||
print_choices();
|
||||
log(" insufficient choices.\n");
|
||||
seldb.erase(sig);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
if (is_onehot && optimize_onehot)
|
||||
{
|
||||
print_choices();
|
||||
if (!onehot_db.query(sig))
|
||||
{
|
||||
log(" failed to detect onehot driver. do not optimize.\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
log(" optimizing one-hot encoding.\n");
|
||||
for (auto &it : choices)
|
||||
{
|
||||
const Const &val = it.first;
|
||||
int index = -1;
|
||||
|
||||
for (int i = 0; i < GetSize(val); i++)
|
||||
if (val[i] == State::S1) {
|
||||
log_assert(index < 0);
|
||||
index = i;
|
||||
}
|
||||
|
||||
if (index < 0) {
|
||||
log(" %3d: zero encoding.\n", it.second);
|
||||
continue;
|
||||
}
|
||||
|
||||
SigBit new_ctrl = sig[index];
|
||||
log(" %3d: new crtl signal is %s.\n", it.second, log_signal(new_ctrl));
|
||||
updated_S[it.second] = new_ctrl;
|
||||
}
|
||||
}
|
||||
seldb.erase(sig);
|
||||
continue;
|
||||
}
|
||||
|
||||
// find the best permutation
|
||||
vector<int> perm_new_from_old(GetSize(sig));
|
||||
Const perm_xormask(State::S0, GetSize(sig));
|
||||
{
|
||||
vector<int> values(GetSize(choices));
|
||||
vector<bool> used_src_columns(GetSize(sig));
|
||||
vector<vector<bool>> columns(GetSize(sig), vector<bool>(GetSize(values)));
|
||||
|
||||
for (int i = 0; i < GetSize(choices); i++) {
|
||||
Const val = choices.element(i)->first;
|
||||
for (int k = 0; k < GetSize(val); k++)
|
||||
if (val[k] == State::S1)
|
||||
columns[k][i] = true;
|
||||
}
|
||||
|
||||
for (int dst_col = GetSize(sig)-1; dst_col >= 0; dst_col--)
|
||||
{
|
||||
int best_src_col = -1;
|
||||
bool best_inv = false;
|
||||
int best_maxval = 0;
|
||||
int best_delta = 0;
|
||||
|
||||
// find best src column for this dst column
|
||||
for (int src_col = 0; src_col < GetSize(sig); src_col++)
|
||||
{
|
||||
if (used_src_columns[src_col])
|
||||
continue;
|
||||
|
||||
int this_maxval = 0;
|
||||
int this_minval = 1 << 30;
|
||||
|
||||
int this_inv_maxval = 0;
|
||||
int this_inv_minval = 1 << 30;
|
||||
|
||||
for (int i = 0; i < GetSize(values); i++)
|
||||
{
|
||||
int val = values[i];
|
||||
int inv_val = val;
|
||||
|
||||
if (columns[src_col][i])
|
||||
val |= 1 << dst_col;
|
||||
else
|
||||
inv_val |= 1 << dst_col;
|
||||
|
||||
this_maxval = std::max(this_maxval, val);
|
||||
this_minval = std::min(this_minval, val);
|
||||
|
||||
this_inv_maxval = std::max(this_inv_maxval, inv_val);
|
||||
this_inv_minval = std::min(this_inv_minval, inv_val);
|
||||
}
|
||||
|
||||
int this_delta = this_maxval - this_minval;
|
||||
int this_inv_delta = this_maxval - this_minval;
|
||||
bool this_inv = false;
|
||||
|
||||
if (this_delta != this_inv_delta)
|
||||
this_inv = this_inv_delta < this_delta;
|
||||
else if (this_maxval != this_inv_maxval)
|
||||
this_inv = this_inv_maxval < this_maxval;
|
||||
|
||||
if (this_inv) {
|
||||
this_delta = this_inv_delta;
|
||||
this_maxval = this_inv_maxval;
|
||||
this_minval = this_inv_minval;
|
||||
}
|
||||
|
||||
bool this_is_better = false;
|
||||
|
||||
if (best_src_col < 0)
|
||||
this_is_better = true;
|
||||
else if (this_delta != best_delta)
|
||||
this_is_better = this_delta < best_delta;
|
||||
else if (this_maxval != best_maxval)
|
||||
this_is_better = this_maxval < best_maxval;
|
||||
else
|
||||
this_is_better = sig[best_src_col] < sig[src_col];
|
||||
|
||||
if (this_is_better) {
|
||||
best_src_col = src_col;
|
||||
best_inv = this_inv;
|
||||
best_maxval = this_maxval;
|
||||
best_delta = this_delta;
|
||||
}
|
||||
}
|
||||
|
||||
used_src_columns[best_src_col] = true;
|
||||
perm_new_from_old[dst_col] = best_src_col;
|
||||
perm_xormask[dst_col] = best_inv ? State::S1 : State::S0;
|
||||
}
|
||||
}
|
||||
|
||||
// permutated sig
|
||||
SigSpec perm_sig(State::S0, GetSize(sig));
|
||||
for (int i = 0; i < GetSize(sig); i++)
|
||||
perm_sig[i] = sig[perm_new_from_old[i]];
|
||||
|
||||
log(" best permutation: %s\n", log_signal(perm_sig));
|
||||
log(" best xor mask: %s\n", log_signal(perm_xormask));
|
||||
|
||||
// permutated choices
|
||||
int min_choice = 1 << 30;
|
||||
int max_choice = -1;
|
||||
dict<Const, int> perm_choices;
|
||||
|
||||
for (auto &it : choices)
|
||||
{
|
||||
Const &old_c = it.first;
|
||||
Const new_c(State::S0, GetSize(old_c));
|
||||
|
||||
for (int i = 0; i < GetSize(old_c); i++)
|
||||
new_c[i] = old_c[perm_new_from_old[i]];
|
||||
|
||||
Const new_c_before_xor = new_c;
|
||||
new_c = const_xor(new_c, perm_xormask, false, false, GetSize(new_c));
|
||||
|
||||
perm_choices[new_c] = it.second;
|
||||
|
||||
min_choice = std::min(min_choice, new_c.as_int());
|
||||
max_choice = std::max(max_choice, new_c.as_int());
|
||||
|
||||
log(" %3d: %s -> %s -> %s: %s\n", it.second, log_signal(old_c), log_signal(new_c_before_xor),
|
||||
log_signal(new_c), log_signal(B.extract(it.second*width, width)));
|
||||
}
|
||||
|
||||
int range_density = 100*GetSize(choices) / (max_choice-min_choice+1);
|
||||
int absolute_density = 100*GetSize(choices) / (max_choice+1);
|
||||
|
||||
log(" choices: %d\n", GetSize(choices));
|
||||
log(" min choice: %d\n", min_choice);
|
||||
log(" max choice: %d\n", max_choice);
|
||||
log(" range density: %d%%\n", range_density);
|
||||
log(" absolute density: %d%%\n", absolute_density);
|
||||
|
||||
bool full_case = (min_choice == 0) && (max_choice == (1 << GetSize(sig))-1) && (max_choice+1 == GetSize(choices));
|
||||
log(" full case: %s\n", full_case ? "true" : "false");
|
||||
|
||||
// check density percentages
|
||||
Const offset(State::S0, GetSize(sig));
|
||||
if (absolute_density < min_density && range_density >= min_density)
|
||||
{
|
||||
offset = Const(min_choice, GetSize(sig));
|
||||
log(" offset: %s\n", log_signal(offset));
|
||||
|
||||
min_choice -= offset.as_int();
|
||||
max_choice -= offset.as_int();
|
||||
|
||||
dict<Const, int> new_perm_choices;
|
||||
for (auto &it : perm_choices)
|
||||
new_perm_choices[const_sub(it.first, offset, false, false, GetSize(sig))] = it.second;
|
||||
perm_choices.swap(new_perm_choices);
|
||||
} else
|
||||
if (absolute_density < min_density) {
|
||||
log(" insufficient density.\n");
|
||||
seldb.erase(sig);
|
||||
continue;
|
||||
}
|
||||
|
||||
// creat cmp signal
|
||||
SigSpec cmp = perm_sig;
|
||||
if (perm_xormask.as_bool())
|
||||
cmp = module->Xor(NEW_ID, cmp, perm_xormask, false, src);
|
||||
if (offset.as_bool())
|
||||
cmp = module->Sub(NEW_ID, cmp, offset, false, src);
|
||||
|
||||
// create enable signal
|
||||
SigBit en = State::S1;
|
||||
if (!full_case) {
|
||||
Const enable_mask(State::S0, max_choice+1);
|
||||
for (auto &it : perm_choices)
|
||||
enable_mask[it.first.as_int()] = State::S1;
|
||||
en = module->addWire(NEW_ID);
|
||||
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
|
||||
}
|
||||
|
||||
// create data signal
|
||||
SigSpec data(State::Sx, (max_choice+1)*extwidth);
|
||||
for (auto &it : perm_choices) {
|
||||
int position = it.first.as_int()*extwidth;
|
||||
int data_index = it.second;
|
||||
data.replace(position, B.extract(data_index*width, width));
|
||||
updated_S[data_index] = State::S0;
|
||||
updated_B.replace(data_index*width, SigSpec(State::Sx, width));
|
||||
}
|
||||
|
||||
// create shiftx cell
|
||||
SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)};
|
||||
SigSpec outsig = module->addWire(NEW_ID, width);
|
||||
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
|
||||
updated_S.append(en);
|
||||
updated_B.append(outsig);
|
||||
log(" created $shiftx cell %s.\n", log_id(c));
|
||||
|
||||
// remove this sig and continue with the next block
|
||||
seldb.erase(sig);
|
||||
}
|
||||
|
||||
// update $pmux cell
|
||||
cell->setPort("\\S", updated_S);
|
||||
cell->setPort("\\B", updated_B);
|
||||
cell->setParam("\\S_WIDTH", GetSize(updated_S));
|
||||
}
|
||||
}
|
||||
}
|
||||
} Pmux2ShiftxPass;
|
||||
|
||||
struct OnehotPass : public Pass {
|
||||
OnehotPass() : Pass("onehot", "optimize $eq cells for onehot signals") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" onehot [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass optimizes $eq cells that compare one-hot signals against constants\n");
|
||||
log("\n");
|
||||
log(" -v, -vv\n");
|
||||
log(" verbose output\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
bool verbose = false;
|
||||
bool verbose_onehot = false;
|
||||
|
||||
log_header(design, "Executing ONEHOT pass.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-v") {
|
||||
verbose = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-vv") {
|
||||
verbose = true;
|
||||
verbose_onehot = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
SigMap sigmap(module);
|
||||
OnehotDatabase onehot_db(module, sigmap);
|
||||
onehot_db.verbose = verbose_onehot;
|
||||
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type != "$eq")
|
||||
continue;
|
||||
|
||||
SigSpec A = sigmap(cell->getPort("\\A"));
|
||||
SigSpec B = sigmap(cell->getPort("\\B"));
|
||||
|
||||
int a_width = cell->getParam("\\A_WIDTH").as_int();
|
||||
int b_width = cell->getParam("\\B_WIDTH").as_int();
|
||||
|
||||
if (a_width < b_width) {
|
||||
bool a_signed = cell->getParam("\\A_SIGNED").as_int();
|
||||
A.extend_u0(b_width, a_signed);
|
||||
}
|
||||
|
||||
if (b_width < a_width) {
|
||||
bool b_signed = cell->getParam("\\B_SIGNED").as_int();
|
||||
B.extend_u0(a_width, b_signed);
|
||||
}
|
||||
|
||||
if (A.is_fully_const())
|
||||
std::swap(A, B);
|
||||
|
||||
if (!B.is_fully_const())
|
||||
continue;
|
||||
|
||||
if (verbose)
|
||||
log("Checking $eq(%s, %s) cell %s/%s.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
|
||||
|
||||
if (!onehot_db.query(A)) {
|
||||
if (verbose)
|
||||
log(" onehot driver test on %s failed.\n", log_signal(A));
|
||||
continue;
|
||||
}
|
||||
|
||||
int index = -1;
|
||||
bool not_onehot = false;
|
||||
|
||||
for (int i = 0; i < GetSize(B); i++) {
|
||||
if (B[i] != State::S1)
|
||||
continue;
|
||||
if (index >= 0)
|
||||
not_onehot = true;
|
||||
index = i;
|
||||
}
|
||||
|
||||
if (index < 0) {
|
||||
if (verbose)
|
||||
log(" not optimizing the zero pattern.\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
SigSpec Y = cell->getPort("\\Y");
|
||||
|
||||
if (not_onehot)
|
||||
{
|
||||
if (verbose)
|
||||
log(" replacing with constant 0 driver.\n");
|
||||
else
|
||||
log("Replacing one-hot $eq(%s, %s) cell %s/%s with constant 0 driver.\n", log_signal(A), log_signal(B), log_id(module), log_id(cell));
|
||||
module->connect(Y, SigSpec(1, GetSize(Y)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SigSpec sig = A[index];
|
||||
if (verbose)
|
||||
log(" replacing with signal %s.\n", log_signal(sig));
|
||||
else
|
||||
log("Replacing one-hot $eq(%s, %s) cell %s/%s with signal %s.\n",log_signal(A), log_signal(B), log_id(module), log_id(cell), log_signal(sig));
|
||||
sig.extend_u0(GetSize(Y));
|
||||
module->connect(Y, sig);
|
||||
}
|
||||
|
||||
module->remove(cell);
|
||||
}
|
||||
}
|
||||
}
|
||||
} OnehotPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
module pmux2shiftx_test (
|
||||
input [2:0] S1,
|
||||
input [5:0] S2,
|
||||
input [1:0] S3,
|
||||
input [9:0] A, B, C, D, D, E, F, G, H,
|
||||
input [9:0] I, J, K, L, M, N, O, P, Q,
|
||||
output reg [9:0] X
|
||||
);
|
||||
always @* begin
|
||||
case (S1)
|
||||
3'd 0: X = A;
|
||||
3'd 1: X = B;
|
||||
3'd 2: X = C;
|
||||
3'd 3: X = D;
|
||||
3'd 4: X = E;
|
||||
3'd 5: X = F;
|
||||
3'd 6: X = G;
|
||||
3'd 7: X = H;
|
||||
endcase
|
||||
case (S2)
|
||||
6'd 45: X = I;
|
||||
6'd 47: X = J;
|
||||
6'd 49: X = K;
|
||||
6'd 55: X = L;
|
||||
6'd 57: X = M;
|
||||
6'd 59: X = N;
|
||||
endcase
|
||||
case (S3)
|
||||
2'd 1: X = O;
|
||||
2'd 2: X = P;
|
||||
2'd 3: X = Q;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
read_verilog pmux2shiftx.v
|
||||
prep
|
||||
design -save gold
|
||||
|
||||
pmux2shiftx -min_density 70
|
||||
|
||||
opt
|
||||
|
||||
stat
|
||||
# show -width
|
||||
select -assert-count 1 t:$sub
|
||||
select -assert-count 2 t:$mux
|
||||
select -assert-count 2 t:$shift
|
||||
select -assert-count 3 t:$shiftx
|
||||
|
||||
design -stash gate
|
||||
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load gold
|
||||
stat
|
||||
|
||||
design -load gate
|
||||
stat
|
||||
Loading…
Reference in New Issue