mirror of https://github.com/YosysHQ/yosys.git
Adjust makefiles to work with out-of-tree builds
This is based on work done by Larry Doolittle
This commit is contained in:
parent
c43f38c81b
commit
e4ef000b70
26
Makefile
26
Makefile
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@ -36,8 +36,10 @@ SMALL = 0
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all: top-all
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YOSYS_SRC := $(shell pwd)
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CXXFLAGS = -Wall -Wextra -ggdb -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(DESTDIR)/include
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YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
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VPATH := $(YOSYS_SRC)
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CXXFLAGS = -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(DESTDIR)/include
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LDFLAGS = -L$(DESTDIR)/lib
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LDLIBS = -lstdc++ -lm
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SED = sed
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@ -190,7 +192,7 @@ define add_share_file
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EXTRA_TARGETS += $(subst //,/,$(1)/$(notdir $(2)))
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$(subst //,/,$(1)/$(notdir $(2))): $(2)
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$$(P) mkdir -p $(1)
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$$(Q) cp $(2) $(subst //,/,$(1)/$(notdir $(2)))
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$$(Q) cp "$(YOSYS_SRC)"/$(2) $(subst //,/,$(1)/$(notdir $(2)))
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endef
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define add_include_file
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@ -250,10 +252,10 @@ OBJS += libs/minisat/SimpSolver.o
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OBJS += libs/minisat/Solver.o
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OBJS += libs/minisat/System.o
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include frontends/*/Makefile.inc
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include passes/*/Makefile.inc
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include backends/*/Makefile.inc
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include techlibs/*/Makefile.inc
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include $(YOSYS_SRC)/frontends/*/Makefile.inc
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include $(YOSYS_SRC)/passes/*/Makefile.inc
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include $(YOSYS_SRC)/backends/*/Makefile.inc
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include $(YOSYS_SRC)/techlibs/*/Makefile.inc
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else
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@ -297,20 +299,22 @@ libyosys.so: $(filter-out kernel/driver.o,$(OBJS))
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$(P) $(CXX) -o libyosys.so -shared -Wl,-soname,libyosys.so $(LDFLAGS) $^ $(LDLIBS)
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%.o: %.cc
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$(Q) mkdir -p $(dir $@)
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$(P) $(CXX) -o $@ -c $(CXXFLAGS) $<
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%.o: %.cpp
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$(Q) mkdir -p $(dir $@)
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$(P) $(CXX) -o $@ -c $(CXXFLAGS) $<
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kernel/version_$(GIT_REV).cc: Makefile
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kernel/version_$(GIT_REV).cc: $(YOSYS_SRC)/Makefile
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$(P) rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc
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$(Q) echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys $(YOSYS_VER) (git sha1 $(GIT_REV), $(notdir $(CXX)) ` \
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$(Q) mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys $(YOSYS_VER) (git sha1 $(GIT_REV), $(notdir $(CXX)) ` \
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$(CXX) --version | tr ' ()' '\n' | grep '^[0-9]' | head -n1` $(filter -f% -m% -O% -DNDEBUG,$(CXXFLAGS)))\"; }" > kernel/version_$(GIT_REV).cc
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yosys-config: misc/yosys-config.in
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$(P) $(SED) -e 's,@CXXFLAGS@,$(subst -I"$(YOSYS_SRC)",-I"$(TARGET_DATDIR)/include",$(CXXFLAGS)),;' \
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$(P) $(SED) -e 's,@CXXFLAGS@,$(subst -I. -I"$(YOSYS_SRC)",-I"$(TARGET_DATDIR)/include",$(CXXFLAGS)),;' \
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-e 's,@CXX@,$(CXX),;' -e 's,@LDFLAGS@,$(LDFLAGS),;' -e 's,@LDLIBS@,$(LDLIBS),;' \
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-e 's,@BINDIR@,$(TARGET_BINDIR),;' -e 's,@DATDIR@,$(TARGET_DATDIR),;' < misc/yosys-config.in > yosys-config
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-e 's,@BINDIR@,$(TARGET_BINDIR),;' -e 's,@DATDIR@,$(TARGET_DATDIR),;' < $< > yosys-config
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$(Q) chmod +x yosys-config
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abc/abc-$(ABCREV)$(EXE):
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@ -5,13 +5,15 @@ GENFILES += frontends/ilang/ilang_parser.output
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GENFILES += frontends/ilang/ilang_lexer.cc
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frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y
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$(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser frontends/ilang/ilang_parser.y
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$(Q) mkdir -p $(dir $@)
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$(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser $<
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$(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc
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frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc
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frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l
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$(P) flex -o frontends/ilang/ilang_lexer.cc frontends/ilang/ilang_lexer.l
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$(Q) mkdir -p $(dir $@)
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$(P) flex -o frontends/ilang/ilang_lexer.cc $<
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OBJS += frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o
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OBJS += frontends/ilang/ilang_frontend.o
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@ -29,7 +29,7 @@
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#pragma clang diagnostic ignored "-Wdeprecated-register"
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#endif
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#include "ilang_frontend.h"
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#include "frontends/ilang/ilang_frontend.h"
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#include "ilang_parser.tab.h"
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USING_YOSYS_NAMESPACE
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@ -24,7 +24,7 @@
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%{
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#include <list>
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#include "ilang_frontend.h"
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#include "frontends/ilang/ilang_frontend.h"
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YOSYS_NAMESPACE_BEGIN
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namespace ILANG_FRONTEND {
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std::istream *lexin;
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@ -5,13 +5,15 @@ GENFILES += frontends/verilog/verilog_parser.output
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GENFILES += frontends/verilog/verilog_lexer.cc
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frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
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$(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y
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$(Q) mkdir -p $(dir $@)
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$(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser $<
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$(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc
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frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc
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frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
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$(P) flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l
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$(Q) mkdir -p $(dir $@)
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$(P) flex -o frontends/verilog/verilog_lexer.cc $<
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OBJS += frontends/verilog/verilog_parser.tab.o
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OBJS += frontends/verilog/verilog_lexer.o
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@ -40,7 +40,7 @@
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#endif
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#include "kernel/log.h"
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#include "verilog_frontend.h"
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#include "frontends/verilog/verilog_frontend.h"
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#include "frontends/ast/ast.h"
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#include "verilog_parser.tab.h"
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@ -36,7 +36,7 @@
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%{
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#include <list>
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#include <string.h>
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#include "verilog_frontend.h"
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#include "frontends/verilog/verilog_frontend.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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@ -24,6 +24,7 @@ endif
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GENFILES += passes/techmap/techmap.inc
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passes/techmap/techmap.inc: techlibs/common/techmap.v
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$(Q) mkdir -p $(dir $@)
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$(P) echo "// autogenerated from $<" > $@.new
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$(Q) echo "static char stdcells_code[] = {" >> $@.new
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$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
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@ -37,6 +38,7 @@ TARGETS += yosys-filterlib$(EXE)
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EXTRA_OBJS += passes/techmap/filterlib.o
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yosys-filterlib$(EXE): passes/techmap/filterlib.o
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$(Q) mkdir -p $(dir $@)
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$(P) $(CXX) -o yosys-filterlib$(EXE) $(LDFLAGS) $^ $(LDLIBS)
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endif
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@ -3,16 +3,9 @@ ifneq ($(SMALL),1)
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OBJS += techlibs/common/synth.o
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endif
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EXTRA_TARGETS += techlibs/common/blackbox.v
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techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/simcells.v
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$(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
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$(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
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$(eval $(call add_share_file,share,techlibs/common/simlib.v))
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$(eval $(call add_share_file,share,techlibs/common/simcells.v))
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$(eval $(call add_share_file,share,techlibs/common/techmap.v))
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$(eval $(call add_share_file,share,techlibs/common/blackbox.v))
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$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
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$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
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$(eval $(call add_share_file,share,techlibs/common/cells.lib))
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@ -1,5 +0,0 @@
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#!/bin/sed -r
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/^(wire|assign|reg|event|integer|localparam|\/\/|[\/ ]\*| *$|`)/ d;
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/^(genvar|generate|always|initial|task|function)/,/^end/ d;
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/^endmodule/ s/$/\n/;
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s/ reg / /;
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@ -11,7 +11,7 @@ EXTRA_OBJS += techlibs/ice40/brams_init.mk
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.SECONDARY: techlibs/ice40/brams_init.mk
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techlibs/ice40/brams_init.mk: techlibs/ice40/brams_init.py
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$(P) cd techlibs/ice40 && python brams_init.py
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$(P) cd share/ice40 && python $<
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$(Q) touch techlibs/ice40/brams_init.mk
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techlibs/ice40/brams_init1.vh: techlibs/ice40/brams_init.mk
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@ -23,7 +23,4 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
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$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_init3.vh))
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@ -10,8 +10,8 @@ EXTRA_OBJS += techlibs/xilinx/brams_init.mk
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.SECONDARY: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py
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$(P) cd techlibs/xilinx && python brams_init.py
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$(Q) touch techlibs/xilinx/brams_init.mk
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$(P) cd share/xilinx && python $<
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$(Q) touch $@
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techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk
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@ -22,10 +22,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
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