mirror of https://github.com/YosysHQ/yosys.git
Minor fixes in handling of "init" attribute
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parent
229825e1b8
commit
d176e613c2
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@ -295,15 +295,15 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
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f << stringf("%s" "output%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
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if (wire->port_input && wire->port_output)
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f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
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if (reg_wires.count(wire->name))
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if (reg_wires.count(wire->name)) {
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f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
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else if (!wire->port_input && !wire->port_output)
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if (wire->attributes.count("\\init")) {
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f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
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dump_const(f, wire->attributes.at("\\init"));
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f << stringf(";\n");
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}
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} else if (!wire->port_input && !wire->port_output)
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f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
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if (wire->attributes.count("\\init")) {
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f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
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dump_const(f, wire->attributes.at("\\init"));
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f << stringf(";\n");
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}
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#endif
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}
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@ -244,6 +244,7 @@ struct ProcArstPass : public Pass {
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}
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extra_args(args, argidx, design);
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pool<Wire*> delete_initattr_wires;
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for (auto mod : design->modules())
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if (design->selected(mod)) {
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@ -265,6 +266,7 @@ struct ProcArstPass : public Pass {
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value.extend_u0(chunk.wire->width, false);
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arst_sig.append(chunk);
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arst_val.append(value.extract(chunk.offset, chunk.width));
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delete_initattr_wires.insert(chunk.wire);
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}
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if (arst_sig.size()) {
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log("Added global reset to process %s: %s <- %s\n",
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@ -281,6 +283,9 @@ struct ProcArstPass : public Pass {
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}
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}
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}
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for (auto wire : delete_initattr_wires)
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wire->attributes.erase("\\init");
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}
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} ProcArstPass;
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