mirror of https://github.com/YosysHQ/yosys.git
Added missing newline to some error messages
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@ -73,10 +73,10 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module,
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log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
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if (tpl->memories.size() != 0)
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log_error("Technology map yielded memories -> this is not supported.");
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log_error("Technology map yielded memories -> this is not supported.\n");
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if (tpl->processes.size() != 0)
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log_error("Technology map yielded processes -> this is not supported.");
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log_error("Technology map yielded processes -> this is not supported.\n");
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for (auto &it : tpl->wires) {
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RTLIL::Wire *w = new RTLIL::Wire(*it.second);
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