mirror of https://github.com/YosysHQ/yosys.git
Using selections in "ls" command
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fb8c755726
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@ -1328,21 +1328,20 @@ struct CdPass : public Pass {
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} CdPass;
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template<typename T>
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static int log_matches(const char *title, std::string pattern, T list)
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static void log_matches(const char *title, Module *module, T list)
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{
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std::vector<RTLIL::IdString> matches;
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std::vector<IdString> matches;
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for (auto &it : list)
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if (pattern.empty() || match_ids(it.first, pattern))
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if (module->selected(it.second))
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matches.push_back(it.first);
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if (matches.empty())
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return 0;
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log("\n%d %s:\n", int(matches.size()), title);
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for (auto &id : matches)
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log(" %s\n", RTLIL::id2cstr(id));
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return matches.size();
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if (!matches.empty()) {
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log("\n%d %s:\n", int(matches.size()), title);
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std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
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for (auto id : matches)
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log(" %s\n", RTLIL::id2cstr(id));
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}
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}
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struct LsPass : public Pass {
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@ -1351,44 +1350,41 @@ struct LsPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ls [pattern]\n");
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log(" ls [selection]\n");
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log("\n");
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log("When no active module is selected, this prints a list of all modules.\n");
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log("When no active module is selected, this prints a list of modules.\n");
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log("\n");
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log("When an active module is selected, this prints a list of objects in the module.\n");
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log("\n");
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log("If a pattern is given, the objects matching the pattern are printed\n");
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log("\n");
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log("Note that this command does not use the selection mechanism and always operates\n");
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log("on the whole design or whole active module. Use 'select -list' to show a list\n");
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log("of currently selected objects.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string pattern;
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int counter = 0;
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if (args.size() != 1 && args.size() != 2)
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log_cmd_error("Invalid number of arguments.\n");
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if (args.size() == 2)
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pattern = args.at(1);
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size_t argidx = 1;
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extra_args(args, argidx, design);
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if (design->selected_active_module.empty())
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{
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counter += log_matches("modules", pattern, design->modules_);
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std::vector<IdString> matches;
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for (auto mod : design->selected_modules())
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matches.push_back(mod->name);
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if (!matches.empty()) {
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log("\n%d %s:\n", int(matches.size()), "modules");
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std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
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for (auto id : matches)
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log(" %s%s\n", log_id(id), design->selected_whole_module(design->module(id)) ? "" : "*");
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}
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}
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else
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if (design->modules_.count(design->selected_active_module) > 0)
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if (design->module(design->selected_active_module) != nullptr)
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{
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RTLIL::Module *module = design->modules_.at(design->selected_active_module);
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counter += log_matches("wires", pattern, module->wires_);
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counter += log_matches("memories", pattern, module->memories);
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counter += log_matches("cells", pattern, module->cells_);
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counter += log_matches("processes", pattern, module->processes);
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RTLIL::Module *module = design->module(design->selected_active_module);
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log_matches("wires", module, module->wires_);
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log_matches("memories", module, module->memories);
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log_matches("cells", module, module->cells_);
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log_matches("processes", module, module->processes);
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}
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// log("\nfound %d item%s.\n", counter, counter == 1 ? "" : "s");
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}
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} LsPass;
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