mirror of https://github.com/YosysHQ/yosys.git
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
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@ -1237,6 +1237,11 @@ struct Abc9Pass : public Pass {
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map_mux16 = true;
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continue;
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}
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if (arg == "-dress") {
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// TODO
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abc_dress = true;
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continue;
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}
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if (arg == "-g" && argidx+1 < args.size()) {
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for (auto g : split_tokens(args[++argidx], ",")) {
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vector<string> gate_list;
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@ -80,6 +80,9 @@ struct SynthXilinxPass : public Pass
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log(" -abc9\n");
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log(" use abc9 instead of abc\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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log("\n");
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@ -142,6 +145,7 @@ struct SynthXilinxPass : public Pass
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std::string edif_file;
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std::string blif_file;
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std::string run_from, run_to;
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std::string abc = "abc";
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bool flatten = false;
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bool retime = false;
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bool vpr = false;
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@ -191,6 +195,10 @@ struct SynthXilinxPass : public Pass
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nodram = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc = "abc9";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -267,7 +275,7 @@ struct SynthXilinxPass : public Pass
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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Pass::call(design, "clean");
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Pass::call(design, "techmap -map +/xilinx/lut_map.v");
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}
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