mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
This commit is contained in:
Clifford Wolf
commit
73bd1d59a7
|
|
@ -246,24 +246,24 @@ struct CellTypes
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cell_types.clear();
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}
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bool cell_known(RTLIL::IdString type)
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bool cell_known(RTLIL::IdString type) const
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{
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return cell_types.count(type) != 0;
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}
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bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
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bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.outputs.count(port) != 0;
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}
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bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
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bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.inputs.count(port) != 0;
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}
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bool cell_evaluable(RTLIL::IdString type)
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bool cell_evaluable(RTLIL::IdString type) const
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{
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.is_evaluable;
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@ -482,4 +482,3 @@ extern CellTypes yosys_celltypes;
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YOSYS_NAMESPACE_END
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#endif
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@ -0,0 +1,317 @@
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/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
|
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* purpose with or without fee is hereby granted, provided that the above
|
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* copyright notice and this permission notice appear in all copies.
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||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SATGEN_ALGO_H
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#define SATGEN_ALGO_H
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include <stack>
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YOSYS_NAMESPACE_BEGIN
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CellTypes comb_cells_filt()
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{
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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return ct;
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}
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struct Netlist {
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RTLIL::Module *module;
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SigMap sigmap;
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CellTypes ct;
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dict<RTLIL::SigBit, Cell *> sigbit_driver_map;
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dict<RTLIL::Cell *, std::set<RTLIL::SigBit>> cell_inputs_map;
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Netlist(RTLIL::Module *module) : module(module), sigmap(module), ct(module->design) { setup_netlist(module, ct); }
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Netlist(RTLIL::Module *module, const CellTypes &ct) : module(module), sigmap(module), ct(ct) { setup_netlist(module, ct); }
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|
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RTLIL::Cell *driver_cell(RTLIL::SigBit sig) const
|
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{
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sig = sigmap(sig);
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if (!sigbit_driver_map.count(sig)) {
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return NULL;
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}
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|
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return sigbit_driver_map.at(sig);
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}
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|
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RTLIL::SigSpec driver_port(RTLIL::SigBit sig)
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{
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RTLIL::Cell *cell = driver_cell(sig);
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|
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if (!cell) {
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return RTLIL::SigSpec();
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}
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for (auto &port : cell->connections_) {
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if (ct.cell_output(cell->type, port.first)) {
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RTLIL::SigSpec port_sig = sigmap(port.second);
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for (int i = 0; i < GetSize(port_sig); i++) {
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if (port_sig[i] == sig) {
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return port.second[i];
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}
|
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}
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}
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}
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return RTLIL::SigSpec();
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}
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|
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void setup_netlist(RTLIL::Module *module, const CellTypes &ct)
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{
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for (auto cell : module->cells()) {
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if (ct.cell_known(cell->type)) {
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std::set<RTLIL::SigBit> inputs, outputs;
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for (auto &port : cell->connections()) {
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std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
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if (ct.cell_output(cell->type, port.first))
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outputs.insert(bits.begin(), bits.end());
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else
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inputs.insert(bits.begin(), bits.end());
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}
|
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cell_inputs_map[cell] = inputs;
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for (auto &bit : outputs) {
|
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sigbit_driver_map[bit] = cell;
|
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};
|
||||
}
|
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}
|
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}
|
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};
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namespace detail
|
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{
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struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, RTLIL::SigBit> {
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using set_iter_t = std::set<RTLIL::SigBit>::iterator;
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|
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const Netlist &net;
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RTLIL::SigBit sig;
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bool sentinel;
|
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CellTypes *cell_filter;
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std::stack<std::pair<set_iter_t, set_iter_t>> dfs_path_stack;
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std::set<RTLIL::Cell *> cells_visited;
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NetlistConeWireIter(const Netlist &net) : net(net), sentinel(true), cell_filter(NULL) {}
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NetlistConeWireIter(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL)
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: net(net), sig(sig), sentinel(false), cell_filter(cell_filter)
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{
|
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}
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|
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const RTLIL::SigBit &operator*() const { return sig; };
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bool operator!=(const NetlistConeWireIter &other) const
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{
|
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if (sentinel || other.sentinel) {
|
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return sentinel != other.sentinel;
|
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} else {
|
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return sig != other.sig;
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}
|
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}
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bool operator==(const NetlistConeWireIter &other) const
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{
|
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if (sentinel || other.sentinel) {
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return sentinel == other.sentinel;
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} else {
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return sig == other.sig;
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}
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}
|
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|
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void next_sig_in_dag()
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{
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while (1) {
|
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if (dfs_path_stack.empty()) {
|
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sentinel = true;
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return;
|
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}
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auto &cell_inputs_iter = dfs_path_stack.top().first;
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auto &cell_inputs_iter_guard = dfs_path_stack.top().second;
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|
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cell_inputs_iter++;
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if (cell_inputs_iter != cell_inputs_iter_guard) {
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sig = *cell_inputs_iter;
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return;
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} else {
|
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dfs_path_stack.pop();
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}
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}
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}
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NetlistConeWireIter &operator++()
|
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{
|
||||
RTLIL::Cell *cell = net.driver_cell(sig);
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|
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if (!cell) {
|
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next_sig_in_dag();
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return *this;
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||||
}
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|
||||
if (cells_visited.count(cell)) {
|
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next_sig_in_dag();
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||||
return *this;
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}
|
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|
||||
if ((cell_filter) && (!cell_filter->cell_known(cell->type))) {
|
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next_sig_in_dag();
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return *this;
|
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}
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auto &inputs = net.cell_inputs_map.at(cell);
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dfs_path_stack.push(std::make_pair(inputs.begin(), inputs.end()));
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cells_visited.insert(cell);
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sig = (*dfs_path_stack.top().first);
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return *this;
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}
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};
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struct NetlistConeWireIterable {
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const Netlist &net;
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RTLIL::SigBit sig;
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CellTypes *cell_filter;
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NetlistConeWireIterable(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) : net(net), sig(sig), cell_filter(cell_filter)
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{
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}
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NetlistConeWireIter begin() { return NetlistConeWireIter(net, sig, cell_filter); }
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NetlistConeWireIter end() { return NetlistConeWireIter(net); }
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};
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struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, RTLIL::Cell *> {
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const Netlist &net;
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NetlistConeWireIter sig_iter;
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NetlistConeCellIter(const Netlist &net) : net(net), sig_iter(net) {}
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NetlistConeCellIter(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) : net(net), sig_iter(net, sig, cell_filter)
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{
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if ((!sig_iter.sentinel) && (!has_driver_cell(*sig_iter))) {
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++(*this);
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}
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}
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bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
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RTLIL::Cell *operator*() const { return net.sigbit_driver_map.at(*sig_iter); };
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bool operator!=(const NetlistConeCellIter &other) const { return sig_iter != other.sig_iter; }
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bool operator==(const NetlistConeCellIter &other) const { return sig_iter == other.sig_iter; }
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NetlistConeCellIter &operator++()
|
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{
|
||||
while (true) {
|
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++sig_iter;
|
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if (sig_iter.sentinel) {
|
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return *this;
|
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}
|
||||
|
||||
RTLIL::Cell* cell = net.driver_cell(*sig_iter);
|
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|
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if (!cell) {
|
||||
continue;
|
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}
|
||||
|
||||
if ((sig_iter.cell_filter) && (!sig_iter.cell_filter->cell_known(cell->type))) {
|
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continue;
|
||||
}
|
||||
|
||||
if (!sig_iter.cells_visited.count(cell)) {
|
||||
return *this;
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
struct NetlistConeCellIterable {
|
||||
const Netlist &net;
|
||||
RTLIL::SigBit sig;
|
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CellTypes *cell_filter;
|
||||
|
||||
NetlistConeCellIterable(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL) : net(net), sig(sig), cell_filter(cell_filter)
|
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{
|
||||
}
|
||||
|
||||
NetlistConeCellIter begin() { return NetlistConeCellIter(net, sig, cell_filter); }
|
||||
NetlistConeCellIter end() { return NetlistConeCellIter(net); }
|
||||
};
|
||||
|
||||
// struct NetlistConeInputsIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
|
||||
// const Netlist &net;
|
||||
// RTLIL::SigBit sig;
|
||||
|
||||
// NetlistConeWireIter sig_iter;
|
||||
|
||||
// bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
|
||||
|
||||
// NetlistConeInputsIter(const Netlist &net, RTLIL::SigBit sig = NULL) : net(net), sig(sig), sig_iter(net, sig)
|
||||
// {
|
||||
// if ((sig != NULL) && (has_driver_cell(sig_iter))) {
|
||||
// ++(*this);
|
||||
// }
|
||||
// }
|
||||
|
||||
// const RTLIL::SigBit &operator*() const { return sig_iter; };
|
||||
// bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; }
|
||||
// bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; }
|
||||
// NetlistConeInputsIter &operator++()
|
||||
// {
|
||||
// do {
|
||||
// ++sig_iter;
|
||||
// if (sig_iter->empty()) {
|
||||
// return *this;
|
||||
// }
|
||||
// } while (has_driver_cell(sig_iter));
|
||||
|
||||
// return *this;
|
||||
// }
|
||||
// };
|
||||
|
||||
// struct NetlistConeInputsIterable {
|
||||
// const Netlist &net;
|
||||
// RTLIL::SigBit sig;
|
||||
|
||||
// NetlistConeInputsIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {}
|
||||
|
||||
// NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, sig); }
|
||||
// NetlistConeInputsIter end() { return NetlistConeInputsIter(net); }
|
||||
// };
|
||||
} // namespace detail
|
||||
|
||||
detail::NetlistConeWireIterable cone(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL)
|
||||
{
|
||||
return detail::NetlistConeWireIterable(net, net.sigmap(sig), cell_filter = cell_filter);
|
||||
}
|
||||
|
||||
// detail::NetlistConeInputsIterable cone_inputs(RTLIL::SigBit sig) { return NetlistConeInputsIterable(this, &sig); }
|
||||
detail::NetlistConeCellIterable cell_cone(const Netlist &net, RTLIL::SigBit sig, CellTypes *cell_filter = NULL)
|
||||
{
|
||||
return detail::NetlistConeCellIterable(net, net.sigmap(sig), cell_filter);
|
||||
}
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
|
|
@ -17,11 +17,14 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include "kernel/log.h"
|
||||
#include <stdlib.h>
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/satgen.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include "netlist.h"
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
|
@ -29,7 +32,11 @@ PRIVATE_NAMESPACE_BEGIN
|
|||
SigMap assign_map, dff_init_map;
|
||||
SigSet<RTLIL::Cell*> mux_drivers;
|
||||
dict<SigBit, pool<SigBit>> init_attributes;
|
||||
std::map<RTLIL::Module*, Netlist> netlists;
|
||||
std::map<RTLIL::Module *, CellTypes> comb_filters;
|
||||
|
||||
bool keepdc;
|
||||
bool sat;
|
||||
|
||||
void remove_init_attr(SigSpec sig)
|
||||
{
|
||||
|
|
@ -452,6 +459,71 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
|
|||
dff->unsetPort("\\E");
|
||||
}
|
||||
|
||||
if (sat && has_init) {
|
||||
bool removed_sigbits = false;
|
||||
|
||||
// Create netlist for the module if not already available
|
||||
if (!netlists.count(mod)) {
|
||||
netlists.emplace(mod, Netlist(mod));
|
||||
comb_filters.emplace(mod, comb_cells_filt());
|
||||
}
|
||||
|
||||
// Load netlist for the module from the pool
|
||||
Netlist &net = netlists.at(mod);
|
||||
|
||||
|
||||
// For each register bit, try to prove that it cannot change from the initial value. If so, remove it
|
||||
for (int position = 0; position < GetSize(sig_d); position += 1) {
|
||||
RTLIL::SigBit q_sigbit = sig_q[position];
|
||||
RTLIL::SigBit d_sigbit = sig_d[position];
|
||||
|
||||
if ((!q_sigbit.wire) || (!d_sigbit.wire)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
ezSatPtr ez;
|
||||
SatGen satgen(ez.get(), &net.sigmap);
|
||||
|
||||
// Create SAT instance only for the cells that influence the register bit combinatorially
|
||||
for (const auto &cell : cell_cone(net, d_sigbit, &comb_filters.at(mod))) {
|
||||
if (!satgen.importCell(cell))
|
||||
log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(cell->name),
|
||||
RTLIL::id2cstr(cell->type));
|
||||
}
|
||||
|
||||
RTLIL::Const sigbit_init_val = val_init.extract(position);
|
||||
int init_sat_pi = satgen.importSigSpec(sigbit_init_val).front();
|
||||
|
||||
int q_sat_pi = satgen.importSigBit(q_sigbit);
|
||||
int d_sat_pi = satgen.importSigBit(d_sigbit);
|
||||
|
||||
// Try to find out whether the register bit can change under some circumstances
|
||||
bool counter_example_found = ez->solve(ez->IFF(q_sat_pi, init_sat_pi), ez->NOT(ez->IFF(d_sat_pi, init_sat_pi)));
|
||||
|
||||
// If the register bit cannot change, we can replace it with a constant
|
||||
if (!counter_example_found) {
|
||||
|
||||
RTLIL::SigSpec driver_port = net.driver_port(q_sigbit);
|
||||
RTLIL::Wire *dummy_wire = mod->addWire(NEW_ID, 1);
|
||||
|
||||
for (auto &conn : mod->connections_)
|
||||
net.sigmap(conn.first).replace(driver_port, dummy_wire, &conn.first);
|
||||
|
||||
remove_init_attr(driver_port);
|
||||
driver_port = dummy_wire;
|
||||
|
||||
mod->connect(RTLIL::SigSig(q_sigbit, sigbit_init_val));
|
||||
|
||||
removed_sigbits = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (removed_sigbits) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return false;
|
||||
|
||||
delete_dff:
|
||||
|
|
@ -467,7 +539,7 @@ struct OptRmdffPass : public Pass {
|
|||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" opt_rmdff [-keepdc] [selection]\n");
|
||||
log(" opt_rmdff [-keepdc] [-sat] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass identifies flip-flops with constant inputs and replaces them with\n");
|
||||
log("a constant driver.\n");
|
||||
|
|
@ -479,6 +551,7 @@ struct OptRmdffPass : public Pass {
|
|||
log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
|
||||
|
||||
keepdc = false;
|
||||
sat = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
|
|
@ -486,12 +559,17 @@ struct OptRmdffPass : public Pass {
|
|||
keepdc = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-sat") {
|
||||
sat = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
netlists.clear();
|
||||
comb_filters.clear();
|
||||
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
for (auto module : design->selected_modules()) {
|
||||
pool<SigBit> driven_bits;
|
||||
dict<SigBit, State> init_bits;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
module top(
|
||||
input clk,
|
||||
input a,
|
||||
output b
|
||||
);
|
||||
reg b_reg;
|
||||
initial begin
|
||||
b_reg <= 0;
|
||||
end
|
||||
|
||||
assign b = b_reg;
|
||||
always @(posedge clk) begin
|
||||
b_reg <= a && b_reg;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
read_verilog opt_ff_sat.v
|
||||
prep -flatten
|
||||
opt_rmdff -sat
|
||||
synth
|
||||
Loading…
Reference in New Issue