mirror of https://github.com/YosysHQ/yosys.git
Added port swapping and compatible types to "extract" pass
This commit is contained in:
Clifford Wolf
parent
08c43f27af
commit
c3cc9839a9
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@ -21,6 +21,7 @@
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "libs/subcircuit/subcircuit.h"
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#include <algorithm>
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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@ -53,14 +54,14 @@ namespace
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graph.createNode("$const$1", "$const$1");
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graph.createNode("$const$x", "$const$x");
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graph.createNode("$const$z", "$const$z");
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graph.createPort("$const$0", "Y", 1);
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graph.createPort("$const$1", "Y", 1);
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graph.createPort("$const$x", "Y", 1);
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graph.createPort("$const$z", "Y", 1);
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graph.markExtern("$const$0", "Y", 0);
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graph.markExtern("$const$1", "Y", 0);
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graph.markExtern("$const$x", "Y", 0);
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graph.markExtern("$const$z", "Y", 0);
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graph.createPort("$const$0", "\\Y", 1);
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graph.createPort("$const$1", "\\Y", 1);
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graph.createPort("$const$x", "\\Y", 1);
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graph.createPort("$const$z", "\\Y", 1);
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graph.markExtern("$const$0", "\\Y", 0);
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graph.markExtern("$const$1", "\\Y", 0);
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graph.markExtern("$const$x", "\\Y", 0);
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graph.markExtern("$const$z", "\\Y", 0);
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}
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// create graph nodes from cells
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@ -93,7 +94,7 @@ namespace
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if (chunk.data.bits[0] == RTLIL::State::S0) node = "$const$0";
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if (chunk.data.bits[0] == RTLIL::State::S1) node = "$const$1";
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if (chunk.data.bits[0] == RTLIL::State::Sz) node = "$const$z";
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graph.createConnection(cell->name, conn.first, i, node, "Y", 0);
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graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0);
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} else
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graph.createConstant(cell->name, conn.first, i, int(chunk.data.bits[0]));
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continue;
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@ -208,9 +209,12 @@ struct ExtractPass : public Pass {
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log_header("Executing EXTRACT pass (map subcircuits to cells).\n");
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log_push();
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SubCircuit::Solver solver;
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std::vector<SubCircuit::Solver::Result> results;
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std::string filename;
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bool verbose = false;
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bool constports = false;
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bool nodefaultswaps = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -219,43 +223,95 @@ struct ExtractPass : public Pass {
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continue;
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}
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if (args[argidx] == "-verbose") {
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verbose = true;
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solver.setVerbose();
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continue;
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}
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if (args[argidx] == "-constports") {
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constports = true;
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continue;
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}
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if (args[argidx] == "-nodefaultswaps") {
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nodefaultswaps = true;
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continue;
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}
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if (args[argidx] == "-compat" && argidx+2 < args.size()) {
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std::string needle_type = RTLIL::escape_id(args[++argidx]);
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std::string haystack_type = RTLIL::escape_id(args[++argidx]);
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solver.addCompatibleTypes(needle_type, haystack_type);
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continue;
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}
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if (args[argidx] == "-swap" && argidx+2 < args.size()) {
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std::string type = RTLIL::escape_id(args[++argidx]);
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std::set<std::string> ports;
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char *ports_str = strdup(args[++argidx].c_str());
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for (char *sptr, *p = strtok_r(ports_str, ",\t\r\n ", &sptr); p != NULL; p = strtok_r(NULL, ",\t\r\n ", &sptr))
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ports.insert(RTLIL::escape_id(p));
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free(ports_str);
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solver.addSwappablePorts(type, ports);
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continue;
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}
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if (args[argidx] == "-perm" && argidx+3 < args.size()) {
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std::string type = RTLIL::escape_id(args[++argidx]);
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std::vector<std::string> map_left, map_right;
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char *left_str = strdup(args[++argidx].c_str());
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char *right_str = strdup(args[++argidx].c_str());
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for (char *sptr, *p = strtok_r(left_str, ",\t\r\n ", &sptr); p != NULL; p = strtok_r(NULL, ",\t\r\n ", &sptr))
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map_left.push_back(RTLIL::escape_id(p));
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for (char *sptr, *p = strtok_r(right_str, ",\t\r\n ", &sptr); p != NULL; p = strtok_r(NULL, ",\t\r\n ", &sptr))
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map_right.push_back(RTLIL::escape_id(p));
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free(left_str);
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free(right_str);
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if (map_left.size() != map_right.size())
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log_cmd_error("Arguments to -perm are not a valid permutation!\n");
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std::map<std::string, std::string> map;
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for (size_t i = 0; i < map_left.size(); i++)
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map[map_left[i]] = map_right[i];
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std::sort(map_left.begin(), map_left.end());
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std::sort(map_right.begin(), map_right.end());
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if (map_left != map_right)
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log_cmd_error("Arguments to -perm are not a valid permutation!\n");
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solver.addSwappablePortsPermutation(type, map);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!nodefaultswaps) {
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solver.addSwappablePorts("$and", "\\A", "\\B");
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solver.addSwappablePorts("$or", "\\A", "\\B");
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solver.addSwappablePorts("$xor", "\\A", "\\B");
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solver.addSwappablePorts("$xnor", "\\A", "\\B");
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solver.addSwappablePorts("$eq", "\\A", "\\B");
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solver.addSwappablePorts("$ne", "\\A", "\\B");
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solver.addSwappablePorts("$add", "\\A", "\\B");
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solver.addSwappablePorts("$mul", "\\A", "\\B");
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solver.addSwappablePorts("$logic_and", "\\A", "\\B");
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solver.addSwappablePorts("$logic_or", "\\A", "\\B");
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solver.addSwappablePorts("$_AND_", "\\A", "\\B");
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solver.addSwappablePorts("$_OR_", "\\A", "\\B");
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solver.addSwappablePorts("$_XOR_", "\\A", "\\B");
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}
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if (filename.empty())
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log_cmd_error("Missing option -map <verilog_or_ilang_file>.\n");
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RTLIL::Design *map = new RTLIL::Design;
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FILE *f = fopen(filename.c_str(), "rt");
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if (f == NULL)
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log_error("Can't open map file `%s'\n", filename.c_str());
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if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
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Frontend::frontend_call(map, f, filename, "ilang");
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else
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Frontend::frontend_call(map, f, filename, "verilog");
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log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
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RTLIL::Design *map = new RTLIL::Design;
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Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
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fclose(f);
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SubCircuit::Solver solver;
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std::vector<SubCircuit::Solver::Result> results;
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if (verbose)
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solver.setVerbose();
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std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
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log_header("Creating graphs for SubCircuit library.\n");
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for (auto &mod_it : map->modules) {
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SubCircuit::Graph mod_graph;
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std::string graph_name = "needle_" + mod_it.first.substr(mod_it.first[0] == '\\' ? 1 : 0);
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std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first);
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log("Creating needle graph %s.\n", graph_name.c_str());
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if (module2graph(mod_graph, mod_it.second, constports)) {
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solver.addGraph(graph_name, mod_graph);
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@ -265,7 +321,7 @@ struct ExtractPass : public Pass {
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for (auto &mod_it : design->modules) {
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SubCircuit::Graph mod_graph;
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std::string graph_name = "haystack_" + mod_it.first.substr(mod_it.first[0] == '\\' ? 1 : 0);
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std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first);
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log("Creating haystack graph %s.\n", graph_name.c_str());
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if (module2graph(mod_graph, mod_it.second, constports, design)) {
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solver.addGraph(graph_name, mod_graph);
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