mirror of https://github.com/YosysHQ/yosys.git
Fixed handling of "keep" attribute on wires in opt_clean
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@ -227,10 +227,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
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std::vector<RTLIL::Wire*> del_wires;
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for (auto &it : module->wires) {
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RTLIL::Wire *wire = it.second;
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if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0) {
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if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) {
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RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
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assign_map.apply(s2);
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if (!used_signals.check_any(s2) && wire->port_id == 0) {
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if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {
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del_wires.push_back(wire);
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} else {
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s1.expand();
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