mirror of https://github.com/YosysHQ/yosys.git
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -1,4 +1,7 @@
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pattern shiftmul
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//
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// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
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//
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state <SigSpec> shamt
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@ -49,12 +52,16 @@ code
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if (GetSize(port(shift, \Y)) > const_factor)
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reject;
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int factor_bits = ceil_log2(const_factor);
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SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
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if (GetSize(shamt) < factor_bits+GetSize(mul_din))
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reject;
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did_something = true;
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log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
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int new_const_factor_log2 = ceil_log2(const_factor);
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int new_const_factor = 1 << new_const_factor_log2;
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int new_const_factor = 1 << factor_bits;
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SigSpec padding(State::Sx, new_const_factor-const_factor);
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SigSpec old_a = port(shift, \A), new_a;
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int trunc = 0;
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@ -73,7 +80,7 @@ code
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if (trunc > 0)
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new_a.remove(GetSize(new_a)-trunc, trunc);
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SigSpec new_b = {port(mul, const_factor_port == \A ? \B : \A), SigSpec(State::S0, new_const_factor_log2)};
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SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
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if (param(shift, \B_SIGNED).as_bool())
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new_b.append(State::S0);
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@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in
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assign o = i[s*W+:W];
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endmodule
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module peepopt_shiftmul_1 (output y, input [2:0] w);
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assign y = 1'b1 >> (w * (3'b110));
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endmodule
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module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
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wire [3:0] t;
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assign t = i * 3;
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