mirror of https://github.com/YosysHQ/yosys.git
Renamed opt_share to opt_merge
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@ -16,13 +16,13 @@ passes that each perform a simple optimization:
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\item Once at the beginning of {\tt opt}:
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\begin{itemize}
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\item {\tt opt\_expr}
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\item {\tt opt\_share -nomux}
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\item {\tt opt\_merge -nomux}
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\end{itemize}
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\item Repeat until result is stable:
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\begin{itemize}
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\item {\tt opt\_muxtree}
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\item {\tt opt\_reduce}
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\item {\tt opt\_share}
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\item {\tt opt\_merge}
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\item {\tt opt\_rmdff}
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\item {\tt opt\_clean}
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\item {\tt opt\_expr}
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@ -130,7 +130,7 @@ This pass identifies unused signals and cells and removes them from the design.
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creates an \B{unused\_bits} attribute on wires with unused bits. This attribute can be
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used for debugging or by other optimization passes.
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\subsection{The opt\_share pass}
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\subsection{The opt\_merge pass}
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This pass performs trivial resource sharing. This means that this pass identifies cells
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with identical inputs and replaces them with a single instance of the cell.
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@ -489,7 +489,7 @@ select.cc}, {\tt show.cc}, \dots) and a couple of other small utility libraries.
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This directory contains a subdirectory for each pass or group of passes. For example as
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of this writing the directory {\tt passes/opt/} contains the code for seven
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passes: {\tt opt}, {\tt opt\_expr}, {\tt opt\_muxtree}, {\tt opt\_reduce},
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{\tt opt\_rmdff}, {\tt opt\_rmunused} and {\tt opt\_share}.
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{\tt opt\_rmdff}, {\tt opt\_rmunused} and {\tt opt\_merge}.
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\item {\tt techlibs/} \\
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This directory contains simulation models and standard implementations for the
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@ -513,7 +513,7 @@ Yosys. So it is not needed to add additional commands to a central list of comma
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\end{sloppypar}
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Good starting points for reading example source code to learn how to write passes
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are {\tt passes/opt/opt\_rmdff.cc} and {\tt passes/opt/opt\_share.cc}.
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are {\tt passes/opt/opt\_rmdff.cc} and {\tt passes/opt/opt\_merge.cc}.
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See the top-level README file for a quick {\it Getting Started} guide and build
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instructions. The Yosys build is based solely on Makefiles.
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@ -145,12 +145,12 @@ is a macro command that calls other commands:
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\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
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opt_expr # const folding and simple expression rewriting
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opt_share -nomux # merging identical cells
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opt_merge -nomux # merging identical cells
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do
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opt_muxtree # remove never-active branches from multiplexer tree
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opt_reduce # consolidate trees of boolean ops to reduce functions
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opt_share # merging identical cells
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opt_merge # merging identical cells
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opt_rmdff # remove/simplify registers with constant inputs
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opt_clean # remove unused objects (cells, wires) from design
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opt_expr # const folding and simple expression rewriting
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@ -746,7 +746,7 @@ struct MemorySharePass : public Pass {
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log("\n");
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log("Note that in addition to the algorithms implemented in this pass, the $memrd\n");
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log("and $memwr cells are also subject to generic resource sharing passes (and other\n");
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log("optimizations) such as opt_share.\n");
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log("optimizations) such as \"share\" and \"opt_merge\".\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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@ -1,6 +1,6 @@
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OBJS += passes/opt/opt.o
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OBJS += passes/opt/opt_share.o
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OBJS += passes/opt/opt_merge.o
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OBJS += passes/opt/opt_muxtree.o
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OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_rmdff.o
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@ -38,12 +38,12 @@ struct OptPass : public Pass {
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log("passes in the following order:\n");
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log("\n");
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log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
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log(" opt_share [-share_all] -nomux\n");
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log(" opt_merge [-share_all] -nomux\n");
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log("\n");
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log(" do\n");
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log(" opt_muxtree\n");
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log(" opt_reduce [-fine] [-full]\n");
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log(" opt_share [-share_all]\n");
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log(" opt_merge [-share_all]\n");
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log(" opt_rmdff\n");
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log(" opt_clean [-purge]\n");
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log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
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@ -53,7 +53,7 @@ struct OptPass : public Pass {
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log("\n");
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log(" do\n");
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log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
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log(" opt_share [-share_all]\n");
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log(" opt_merge [-share_all]\n");
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log(" opt_rmdff\n");
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log(" opt_clean [-purge]\n");
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log(" while <changed design in opt_rmdff>\n");
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@ -68,7 +68,7 @@ struct OptPass : public Pass {
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std::string opt_clean_args;
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std::string opt_expr_args;
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std::string opt_reduce_args;
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std::string opt_share_args;
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std::string opt_merge_args;
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bool fast_mode = false;
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log_header("Executing OPT pass (performing simple optimizations).\n");
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@ -111,7 +111,7 @@ struct OptPass : public Pass {
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continue;
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}
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if (args[argidx] == "-share_all") {
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opt_share_args += " -share_all";
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opt_merge_args += " -share_all";
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continue;
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}
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if (args[argidx] == "-fast") {
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@ -126,7 +126,7 @@ struct OptPass : public Pass {
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{
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while (1) {
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Pass::call(design, "opt_expr" + opt_expr_args);
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Pass::call(design, "opt_share" + opt_share_args);
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Pass::call(design, "opt_merge" + opt_merge_args);
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design->scratchpad_unset("opt.did_something");
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Pass::call(design, "opt_rmdff");
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if (design->scratchpad_get_bool("opt.did_something") == false)
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@ -139,12 +139,12 @@ struct OptPass : public Pass {
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else
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{
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Pass::call(design, "opt_expr" + opt_expr_args);
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Pass::call(design, "opt_share -nomux" + opt_share_args);
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Pass::call(design, "opt_merge -nomux" + opt_merge_args);
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while (1) {
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design->scratchpad_unset("opt.did_something");
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Pass::call(design, "opt_muxtree");
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Pass::call(design, "opt_reduce" + opt_reduce_args);
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Pass::call(design, "opt_share" + opt_share_args);
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Pass::call(design, "opt_merge" + opt_merge_args);
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Pass::call(design, "opt_rmdff");
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Pass::call(design, "opt_clean" + opt_clean_args);
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Pass::call(design, "opt_expr" + opt_expr_args);
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@ -31,7 +31,7 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptShareWorker
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struct OptMergeWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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@ -212,14 +212,14 @@ struct OptShareWorker
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}
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struct CompareCells {
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OptShareWorker *that;
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CompareCells(OptShareWorker *that) : that(that) {}
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OptMergeWorker *that;
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CompareCells(OptMergeWorker *that) : that(that) {}
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bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
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return that->compare_cells(cell1, cell2);
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}
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};
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OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
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OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
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design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
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{
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total_count = 0;
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@ -286,13 +286,13 @@ struct OptShareWorker
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}
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};
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struct OptSharePass : public Pass {
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OptSharePass() : Pass("opt_share", "consolidate identical cells") { }
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struct OptMergePass : public Pass {
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OptMergePass() : Pass("opt_merge", "consolidate identical cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_share [options] [selection]\n");
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log(" opt_merge [options] [selection]\n");
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log("\n");
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log("This pass identifies cells with identical type and input signals. Such cells\n");
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log("are then merged to one cell.\n");
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@ -328,7 +328,7 @@ struct OptSharePass : public Pass {
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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OptShareWorker worker(design, module, mode_nomux, mode_share_all);
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OptMergeWorker worker(design, module, mode_nomux, mode_share_all);
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total_count += worker.total_count;
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}
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@ -336,6 +336,6 @@ struct OptSharePass : public Pass {
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design->scratchpad_set_bool("opt.did_something", true);
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log("Removed a total of %d cells.\n", total_count);
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}
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} OptSharePass;
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} OptMergePass;
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PRIVATE_NAMESPACE_END
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@ -128,7 +128,7 @@ struct Ice40OptPass : public Pass {
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log(" do\n");
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log(" <ice40 specific optimizations>\n");
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log(" opt_expr -mux_undef -undriven [-full]\n");
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log(" opt_share\n");
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log(" opt_merge\n");
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log(" opt_rmdff\n");
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log(" opt_clean\n");
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log(" while <changed design>\n");
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@ -159,7 +159,7 @@ struct Ice40OptPass : public Pass {
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run_ice40_opts(module);
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Pass::call(design, "opt_expr " + opt_expr_args);
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Pass::call(design, "opt_share");
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Pass::call(design, "opt_merge");
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Pass::call(design, "opt_rmdff");
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Pass::call(design, "opt_clean");
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