mirror of https://github.com/YosysHQ/yosys.git
Allow adders/accumulators with 33 bits using CO output
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@ -56,8 +56,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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return;
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}
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if (GetSize(st.sigO) > 32) {
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log(" accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigO), GetSize(st.sigO));
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if (GetSize(st.sigO) > 33) {
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log(" adder/accumulator (%s) is too large (%d > 33).\n", log_signal(st.sigO), GetSize(st.sigO));
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return;
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}
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@ -137,7 +137,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
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cell->setPort("\\CI", State::Sx);
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cell->setPort("\\CO", pm.module->addWire(NEW_ID));
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cell->setPort("\\ACCUMCI", State::Sx);
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cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
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@ -145,6 +144,12 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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// SB_MAC16 Output Interface
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SigSpec O = st.sigO;
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if (GetSize(O) == 33)
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cell->setPort("\\CO", st.sigO[32]);
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else {
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log_assert(GetSize(O) <= 32);
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cell->setPort("\\CO", pm.module->addWire(NEW_ID));
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}
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if (GetSize(O) < 32)
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O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
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