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Various RTLIL::SigSpec related code cleanups

This commit is contained in:
Clifford Wolf 2014-07-25 14:23:31 +02:00
parent c762050e7f
commit 5826670009
4 changed files with 55 additions and 47 deletions
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42
backends/btor/btor.cc
View File

@ -207,15 +207,15 @@ struct BtorDumper
int start_bit=0;
for(unsigned j=0; j<cell_output->chunks().size(); ++j)
{
start_bit+=cell_output->chunks()[j].width;
if(cell_output->chunks()[j].wire->name == wire->name)
start_bit+=cell_output->chunks().at(j).width;
if(cell_output->chunks().at(j).wire->name == wire->name)
{
prev_wire_line = wire_line;
wire_line = ++line_num;
str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks()[j].width,
cell_line, start_bit-1, start_bit-cell_output->chunks()[j].width);
str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks().at(j).width,
cell_line, start_bit-1, start_bit-cell_output->chunks().at(j).width);
fprintf(f, "%s\n", str.c_str());
wire_width += cell_output->chunks()[j].width;
wire_width += cell_output->chunks().at(j).width;
if(prev_wire_line!=0)
{
++line_num;
@ -320,21 +320,21 @@ struct BtorDumper
auto it = sig_ref.find(s);
if(it == std::end(sig_ref))
{
if (s.chunks().size() == 1)
if (s.is_chunk())
{
l = dump_sigchunk(&s.chunks()[0]);
l = dump_sigchunk(&s.chunks().front());
}
else
{
int l1, l2, w1, w2;
l1 = dump_sigchunk(&s.chunks()[0]);
l1 = dump_sigchunk(&s.chunks().front());
log_assert(l1>0);
w1 = s.chunks()[0].width;
w1 = s.chunks().front().width;
for (unsigned i=1; i < s.chunks().size(); ++i)
{
l2 = dump_sigchunk(&s.chunks()[i]);
l2 = dump_sigchunk(&s.chunks().at(i));
log_assert(l2>0);
w2 = s.chunks()[i].width;
w2 = s.chunks().at(i).width;
++line_num;
str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
fprintf(f, "%s\n", str.c_str());
@ -651,9 +651,9 @@ struct BtorDumper
unsigned start_bit = 0;
for(unsigned i=0; i<cell_output->chunks().size(); ++i)
{
output_width = cell_output->chunks()[i].width;
log_assert( output_width == cell_output->chunks()[i].wire->width);//full reg is given the next value
int reg = dump_wire(cell_output->chunks()[i].wire);//register
output_width = cell_output->chunks().at(i).width;
log_assert( output_width == cell_output->chunks().at(i).wire->width);//full reg is given the next value
int reg = dump_wire(cell_output->chunks().at(i).wire);//register
int slice = value;
if(cell_output->chunks().size()>1)
{
@ -845,9 +845,9 @@ struct BtorDumper
{
for(unsigned i=0; i<output_sig->chunks().size(); ++i)
{
RTLIL::Wire *w = output_sig->chunks()[i].wire;
RTLIL::Wire *w = output_sig->chunks().at(i).wire;
RTLIL::IdString wire_id = w->name;
inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks().at(i)));
}
}
else if(cell->type == "$memwr")
@ -856,12 +856,12 @@ struct BtorDumper
}
else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
{
RTLIL::IdString wire_id = output_sig->chunks()[0].wire->name;
RTLIL::IdString wire_id = output_sig->chunks().front().wire->name;
for(unsigned i=0; i<output_sig->chunks().size(); ++i)
{
RTLIL::Wire *w = output_sig->chunks()[i].wire;
RTLIL::Wire *w = output_sig->chunks().at(i).wire;
RTLIL::IdString wire_id = w->name;
inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks().at(i)));
basic_wires[wire_id] = true;
}
}
@ -869,9 +869,9 @@ struct BtorDumper
{
for(unsigned i=0; i<output_sig->chunks().size(); ++i)
{
RTLIL::Wire *w = output_sig->chunks()[i].wire;
RTLIL::Wire *w = output_sig->chunks().at(i).wire;
RTLIL::IdString wire_id = w->name;
inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks().at(i)));
}
}
}

4
backends/ilang/ilang_backend.cc
View File

@ -102,8 +102,8 @@ void ILANG_BACKEND::dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool au
void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint)
{
if (sig.chunks().size() == 1) {
dump_sigchunk(f, sig.chunks().front(), autoint);
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk(), autoint);
} else {
fprintf(f, "{ ");
for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {

50
backends/verilog/verilog_backend.cc
View File

@ -133,18 +133,23 @@ std::string id(std::string internal_id, bool may_rename = true)
bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
{
if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL)
if (!sig.is_chunk() || sig.as_chunk().wire == NULL)
return false;
if (reg_wires.count(sig.chunks()[0].wire->name) == 0)
RTLIL::SigChunk chunk = sig.as_chunk();
if (reg_wires.count(chunk.wire->name) == 0)
return false;
reg_name = id(sig.chunks()[0].wire->name);
if (sig.size() != sig.chunks()[0].wire->width) {
reg_name = id(chunk.wire->name);
if (sig.size() != chunk.wire->width) {
if (sig.size() == 1)
reg_name += stringf("[%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset);
reg_name += stringf("[%d]", chunk.wire->start_offset + chunk.offset);
else
reg_name += stringf("[%d:%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset + sig.chunks()[0].width - 1,
sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset);
reg_name += stringf("[%d:%d]", chunk.wire->start_offset + chunk.offset + chunk.width - 1,
chunk.wire->start_offset + chunk.offset);
}
return true;
}
@ -220,8 +225,8 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals
void dump_sigspec(FILE *f, RTLIL::SigSpec &sig)
{
if (sig.chunks().size() == 1) {
dump_sigchunk(f, sig.chunks()[0]);
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
} else {
fprintf(f, "{ ");
for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {
@ -299,10 +304,10 @@ std::string cellname(RTLIL::Cell *cell)
if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0)
{
RTLIL::SigSpec sig = cell->connections["\\Q"];
if (sig.size() != 1 || sig.is_fully_const())
if (SIZE(sig) != 1 || sig.is_fully_const())
goto no_special_reg_name;
RTLIL::Wire *wire = sig.chunks()[0].wire;
RTLIL::Wire *wire = sig[0].wire;
if (wire->name[0] != '\\')
goto no_special_reg_name;
@ -316,7 +321,7 @@ std::string cellname(RTLIL::Cell *cell)
cell_name = cell_name + "_reg";
if (wire->width != 1)
cell_name += stringf("[%d]", wire->start_offset + sig.chunks()[0].offset);
cell_name += stringf("[%d]", wire->start_offset + sig[0].offset);
if (active_module && active_module->count_id(cell_name) > 0)
goto no_special_reg_name;
@ -809,9 +814,9 @@ void case_body_find_regs(RTLIL::CaseRule *cs)
case_body_find_regs(*it2);
for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) {
for (size_t i = 0; i < it->first.chunks().size(); i++)
if (it->first.chunks()[i].wire)
reg_wires.insert(it->first.chunks()[i].wire->name);
for (auto &c : it->first.chunks())
if (c.wire != NULL)
reg_wires.insert(c.wire->name);
}
}
@ -821,9 +826,9 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r
case_body_find_regs(&proc->root_case);
for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++)
for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
for (size_t i = 0; i < it2->first.chunks().size(); i++)
if (it2->first.chunks()[i].wire)
reg_wires.insert(it2->first.chunks()[i].wire->name);
for (auto &c : it2->first.chunks())
if (c.wire != NULL)
reg_wires.insert(c.wire->name);
}
return;
}
@ -908,9 +913,12 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
RTLIL::SigSpec sig = cell->connections["\\Q"];
if (sig.chunks().size() == 1 && sig.chunks()[0].wire)
for (int i = 0; i < sig.chunks()[0].width; i++)
reg_bits.insert(std::pair<RTLIL::Wire*,int>(sig.chunks()[0].wire, sig.chunks()[0].offset+i));
if (sig.is_chunk()) {
RTLIL::SigChunk chunk = sig.as_chunk();
if (chunk.wire != NULL)
for (int i = 0; i < chunk.width; i++)
reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i));
}
}
for (auto &it : module->wires)
{

6
passes/cmds/show.cc
View File

@ -171,13 +171,13 @@ struct ShowWorker
std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true)
{
if (sig.chunks().size() == 0) {
if (SIZE(sig) == 0) {
fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
return stringf("v%d", single_idx_count++);
}
if (sig.chunks().size() == 1) {
const RTLIL::SigChunk &c = sig.chunks().front();
if (sig.is_chunk()) {
const RTLIL::SigChunk &c = sig.as_chunk();
if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name));