mirror of https://github.com/YosysHQ/yosys.git
Added RTLIL::SigSpec is_chunk()/as_chunk() API
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@ -2007,6 +2007,14 @@ bool RTLIL::SigSpec::is_wire() const
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return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
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}
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bool RTLIL::SigSpec::is_chunk() const
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{
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cover("kernel.rtlil.sigspec.is_chunk");
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pack();
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return SIZE(chunks_) == 1;
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}
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bool RTLIL::SigSpec::is_fully_const() const
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{
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cover("kernel.rtlil.sigspec.is_fully_const");
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@ -2121,6 +2129,15 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const
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return chunks_[0].wire;
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}
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RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
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{
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cover("kernel.rtlil.sigspec.as_chunk");
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pack();
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assert(is_chunk());
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return chunks_[0];
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}
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bool RTLIL::SigSpec::match(std::string pattern) const
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{
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cover("kernel.rtlil.sigspec.match");
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@ -577,6 +577,8 @@ public:
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inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }
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bool is_wire() const;
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bool is_chunk() const;
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bool is_fully_const() const;
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bool is_fully_def() const;
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bool is_fully_undef() const;
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@ -587,6 +589,7 @@ public:
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std::string as_string() const;
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RTLIL::Const as_const() const;
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RTLIL::Wire *as_wire() const;
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RTLIL::SigChunk as_chunk() const;
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bool match(std::string pattern) const;
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