mirror of https://github.com/YosysHQ/yosys.git
Trim msb/lsb zero bits from full adder in maccmap
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6747a7047e
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1a88e47396
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@ -85,12 +85,34 @@ struct MaccmapWorker
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void fulladd(RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2)
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{
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RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2);
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out1 = module->Xor(NEW_ID, t1, in3);
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int start_index = 0, stop_index = SIZE(in1);
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RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2);
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RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1);
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out2 = module->Or(NEW_ID, t2, t3);
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while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
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start_index++;
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while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
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stop_index--;
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if (start_index == stop_index)
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{
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out1 = RTLIL::SigSpec(0, SIZE(in1));
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out2 = RTLIL::SigSpec(0, SIZE(in1));
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}
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else
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{
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RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, SIZE(in1)-stop_index);
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in1 = in1.extract(start_index, stop_index-start_index);
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in2 = in2.extract(start_index, stop_index-start_index);
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in3 = in3.extract(start_index, stop_index-start_index);
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RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2);
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out1 = {out_zeros_msb, module->Xor(NEW_ID, t1, in3), out_zeros_lsb};
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RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2);
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RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1);
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out2 = {out_zeros_msb, module->Or(NEW_ID, t2, t3), out_zeros_lsb};
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}
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}
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int tree_bit_slots(int n)
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