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Connections between inputs and inouts are driven by the input

This commit is contained in:
Clifford Wolf 2016-04-26 19:49:05 +02:00
parent 958fb29c76
commit 0d2923cccd
1 changed files with 3 additions and 0 deletions
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3
passes/opt/opt_clean.cc
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@ -156,6 +156,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
if (w1->port_input != w2->port_input)
return w2->port_input;
if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
return !(w2->port_input && w2->port_output);
if (w1->name[0] == '\\' && w2->name[0] == '\\') {
if (regs.check_any(s1) != regs.check_any(s2))
return regs.check_any(s2);