mirror of https://github.com/YosysHQ/yosys.git
Add async2sync pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
65234d4b24
commit
87aef8f0cc
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@ -7,4 +7,5 @@ OBJS += passes/sat/miter.o
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OBJS += passes/sat/expose.o
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OBJS += passes/sat/assertpmux.o
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OBJS += passes/sat/clk2fflogic.o
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OBJS += passes/sat/async2sync.o
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@ -0,0 +1,147 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Async2syncPass : public Pass {
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Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" async2sync [options] [selection]\n");
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log("\n");
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log("This command replaces async FF inputs with sync circuits emulating the same\n");
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log("behavior for when the async signals are actually synchronized to the clock.\n");
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log("\n");
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log("This pass assumes negative hold time for the async FF inputs. For example when\n");
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log("a reset deasserts with the clock edge, then the FF output will still drive the\n");
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log("reset value in the next cycle regardless of the data-in value at the time of\n");
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log("the clock edge.\n");
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log("\n");
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log("Currently only $adff cells are supported by this pass.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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// bool flag_noinit = false;
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log_header(design, "Executing ASYNC2SYNC pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-noinit") {
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// flag_noinit = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, State> initbits;
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pool<SigBit> del_initbits;
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for (auto wire : module->wires())
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if (wire->attributes.count("\\init") > 0)
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{
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Const initval = wire->attributes.at("\\init");
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SigSpec initsig = sigmap(wire);
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for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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initbits[initsig[i]] = initval[i];
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}
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for (auto cell : vector<Cell*>(module->selected_cells()))
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{
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if (cell->type.in("$adff"))
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{
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// bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
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bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool();
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Const arst_val = cell->parameters["\\ARST_VALUE"];
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SigSpec sig_clk = cell->getPort("\\CLK");
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SigSpec sig_arst = cell->getPort("\\ARST");
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SigSpec sig_d = cell->getPort("\\D");
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SigSpec sig_q = cell->getPort("\\Q");
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log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(sig_arst), log_signal(sig_d), log_signal(sig_q));
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Const init_val;
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for (int i = 0; i < GetSize(sig_q); i++) {
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SigBit bit = sigmap(sig_q[i]);
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init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
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del_initbits.insert(bit);
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}
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Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
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Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
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new_q->attributes["\\init"] = init_val;
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if (arst_pol) {
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module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
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module->addMux(NEW_ID, new_q, arst_val, sig_arst, sig_q);
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} else {
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module->addMux(NEW_ID, arst_val, sig_d, sig_arst, new_d);
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module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
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}
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cell->setPort("\\D", new_d);
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cell->setPort("\\Q", new_q);
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cell->unsetPort("\\ARST");
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cell->unsetParam("\\ARST_POLARITY");
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cell->unsetParam("\\ARST_VALUE");
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cell->type = "$dff";
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continue;
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}
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}
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for (auto wire : module->wires())
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if (wire->attributes.count("\\init") > 0)
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{
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bool delete_initattr = true;
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Const initval = wire->attributes.at("\\init");
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SigSpec initsig = sigmap(wire);
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for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
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if (del_initbits.count(initsig[i]) > 0)
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initval[i] = State::Sx;
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else if (initval[i] != State::Sx)
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delete_initattr = false;
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if (delete_initattr)
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wire->attributes.erase("\\init");
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else
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wire->attributes.at("\\init") = initval;
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}
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}
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}
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} Async2syncPass;
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PRIVATE_NAMESPACE_END
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