mirror of https://github.com/YosysHQ/yosys.git
opt_lut: new pass, to combine LUTs for tighter packing.
This commit is contained in:
whitequark
parent
1719aa88ac
commit
9e072ec21f
3
Makefile
3
Makefile
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@ -160,7 +160,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
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else ifeq ($(CONFIG),gcc-static)
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LD = $(CXX)
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LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static
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LDLIBS := $(filter-out -lrt,$(LDLIBS))
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LDLIBS := $(filter-out -lrt,$(LDLIBS))
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CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
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CXXFLAGS += -std=c++11 -Os
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ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
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@ -578,6 +578,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/various && bash run-test.sh
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+cd tests/sat && bash run-test.sh
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+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
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+cd tests/opt && bash run-test.sh
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@echo ""
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@echo " Passed \"make test\"."
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@echo ""
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@ -6,6 +6,7 @@ OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_rmdff.o
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OBJS += passes/opt/opt_clean.o
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OBJS += passes/opt/opt_expr.o
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OBJS += passes/opt/opt_lut.o
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ifneq ($(SMALL),1)
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OBJS += passes/opt/share.o
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@ -0,0 +1,274 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2018 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static bool evaluate_lut(SigMap &sigmap, RTLIL::Cell *lut, dict<SigBit, bool> inputs)
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{
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SigSpec lut_input = sigmap(lut->getPort("\\A"));
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int lut_width = lut->getParam("\\WIDTH").as_int();
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Const lut_table = lut->getParam("\\LUT");
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int lut_index = 0;
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for (int i = 0; i < lut_width; i++)
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{
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SigBit input = sigmap(lut_input[i]);
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if (inputs.count(input))
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{
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lut_index |= inputs[input] << i;
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}
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else
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{
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lut_index |= SigSpec(lut_input[i]).as_bool() << i;
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}
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}
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return lut_table.extract(lut_index).as_int();
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}
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static void run_lut_opts(Module *module)
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{
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ModIndex index(module);
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SigMap sigmap(module);
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log("Discovering LUTs.\n");
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pool<RTLIL::Cell*> luts;
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dict<RTLIL::Cell*, int> luts_arity;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$lut")
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{
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int lut_width = cell->getParam("\\WIDTH").as_int();
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SigSpec lut_input = cell->getPort("\\A");
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int lut_arity = 0;
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for (auto &bit : lut_input)
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{
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if (bit.wire)
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lut_arity++;
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}
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log("Found $lut cell %s.%s with WIDTH=%d implementing %d-LUT.\n", log_id(module), log_id(cell), lut_width, lut_arity);
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luts.insert(cell);
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luts_arity[cell] = lut_arity;
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}
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}
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log("\n");
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log("Combining LUTs.\n");
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pool<RTLIL::Cell*> worklist = luts;
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while (worklist.size())
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{
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auto lutA = worklist.pop();
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SigSpec lutA_input = sigmap(lutA->getPort("\\A"));
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SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
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int lutA_width = lutA->getParam("\\WIDTH").as_int();
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int lutA_arity = luts_arity[lutA];
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auto lutA_output_ports = index.query_ports(lutA->getPort("\\Y"));
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if (lutA_output_ports.size() != 2)
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continue;
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for (auto port : lutA_output_ports)
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{
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if (port.cell == lutA)
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continue;
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if (luts.count(port.cell))
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{
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auto lutB = port.cell;
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SigSpec lutB_input = sigmap(lutB->getPort("\\A"));
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SigSpec lutB_output = sigmap(lutB->getPort("\\Y")[0]);
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int lutB_width = lutB->getParam("\\WIDTH").as_int();
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int lutB_arity = luts_arity[lutB];
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log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
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pool<SigBit> lutA_inputs;
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pool<SigBit> lutB_inputs;
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for (auto &bit : lutA_input)
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{
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if (bit.wire)
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lutA_inputs.insert(sigmap(bit));
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}
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for (auto &bit : lutB_input)
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{
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if(bit.wire)
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lutB_inputs.insert(sigmap(bit));
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}
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pool<SigBit> common_inputs;
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for (auto &bit : lutA_inputs)
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{
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if (lutB_inputs.count(bit))
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common_inputs.insert(bit);
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}
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int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
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log(" Cell A is a %d-LUT. Cell B is a %d-LUT. Cells share %zu input(s) and can be merged into one %d-LUT.\n", lutA_arity, lutB_arity, common_inputs.size(), lutM_arity);
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int combine = -1;
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if (combine == -1)
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{
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if (lutM_arity > lutA_width)
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{
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log(" Not combining LUTs into cell A (combined LUT too wide).\n");
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}
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else if (lutB->get_bool_attribute("\\lut_keep"))
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{
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log(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
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}
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else combine = 0;
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}
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if (combine == -1)
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{
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if (lutM_arity > lutB_width)
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{
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log(" Not combining LUTs into cell B (combined LUT too wide).\n");
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}
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else if (lutA->get_bool_attribute("\\lut_keep"))
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{
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log(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
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}
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else combine = 1;
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}
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RTLIL::Cell *lutM, *lutR;
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pool<SigBit> lutM_inputs, lutR_inputs;
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if (combine == 0)
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{
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log(" Combining LUTs into cell A.\n");
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lutM = lutA;
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lutM_inputs = lutA_inputs;
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lutR = lutB;
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lutR_inputs = lutB_inputs;
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}
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else if (combine == 1)
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{
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log(" Combining LUTs into cell B.\n");
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lutM = lutB;
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lutM_inputs = lutB_inputs;
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lutR = lutA;
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lutR_inputs = lutA_inputs;
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}
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else
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{
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log(" Cannot combine LUTs.\n");
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continue;
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}
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pool<SigBit> lutR_unique;
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for (auto &bit : lutR_inputs)
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{
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if (!common_inputs.count(bit) && bit != lutA_output)
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lutR_unique.insert(bit);
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}
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int lutM_width = lutM->getParam("\\WIDTH").as_int();
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SigSpec lutM_input = sigmap(lutM->getPort("\\A"));
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std::vector<SigBit> lutM_new_inputs;
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for (int i = 0; i < lutM_width; i++)
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{
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if ((!lutM_input[i].wire || sigmap(lutM_input[i]) == lutA_output) && lutR_unique.size())
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{
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SigBit new_input = lutR_unique.pop();
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log(" Connecting input %d as %s.\n", i, log_signal(new_input));
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lutM_new_inputs.push_back(new_input);
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}
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else if (sigmap(lutM_input[i]) == lutA_output)
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{
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log(" Disconnecting input %d.\n", i);
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lutM_new_inputs.push_back(SigBit());
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}
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else
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{
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log(" Leaving input %d as %s.\n", i, log_signal(lutM_input[i]));
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lutM_new_inputs.push_back(lutM_input[i]);
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}
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}
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log_assert(lutR_unique.size() == 0);
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RTLIL::Const lutM_new_table(State::Sx, 1 << lutM_width);
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for (int eval = 0; eval < 1 << lutM_width; eval++)
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{
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dict<SigBit, bool> eval_inputs;
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for (size_t i = 0; i < lutM_new_inputs.size(); i++)
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{
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eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
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}
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eval_inputs[lutA_output] = evaluate_lut(sigmap, lutA, eval_inputs);
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lutM_new_table[eval] = (RTLIL::State) evaluate_lut(sigmap, lutB, eval_inputs);
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}
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log(" Old truth table: %s.\n", lutM->getParam("\\LUT").as_string().c_str());
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log(" New truth table: %s.\n", lutM_new_table.as_string().c_str());
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lutM->setParam("\\LUT", lutM_new_table);
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lutM->setPort("\\A", lutM_new_inputs);
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lutM->setPort("\\Y", lutB_output);
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luts_arity[lutM] = lutM_arity;
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luts.erase(lutR);
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luts_arity.erase(lutR);
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lutR->module->remove(lutR);
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worklist.insert(lutM);
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worklist.erase(lutR);
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}
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}
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}
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}
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struct OptLutPass : public Pass {
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OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" opt_lut [options] [selection]\n");
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log("\n");
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log("This pass combines cascaded $lut cells with unused inputs.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-???") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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run_lut_opts(module);
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}
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} OptLutPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1 @@
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*.log
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@ -0,0 +1,3 @@
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module SB_CARRY (output CO, input I0, I1, CI);
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assign CO = (I0 && I1) || ((I0 || I1) && CI);
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endmodule
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@ -0,0 +1,18 @@
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module top(
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input [8:0] a,
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input [8:0] b,
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output [8:0] o1,
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output [2:0] o2,
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input [2:0] c,
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input [2:0] d,
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output [2:0] o3,
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output [2:0] o4,
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input s
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);
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assign o1 = (s ? 0 : a + b);
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assign o2 = (s ? a : a - b);
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assign o3 = (s ? 4'b1111 : d + c);
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assign o4 = (s ? d : c - d);
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endmodule
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@ -0,0 +1,15 @@
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read_verilog opt_lut.v
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synth_ice40
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ice40_unlut
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design -save preopt
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opt_lut
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design -stash postopt
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design -copy-from preopt -as preopt top
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design -copy-from postopt -as postopt top
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equiv_make preopt postopt equiv
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techmap -map ice40_carry.v
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prep -flatten -top equiv
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equiv_induct
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equiv_status -assert
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@ -0,0 +1,6 @@
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#!/bin/bash
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set -e
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for x in *.ys; do
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echo "Running $x.."
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../../yosys -ql ${x%.ys}.log $x
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done
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