riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Revert 90be0d8 as it causes endless loops for some designs

This commit is contained in:
Clifford Wolf 2017-10-14 11:57:04 +02:00
parent 1954c78ea7
commit 716dbc9274
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
passes/opt/opt_reduce.cc
View File

@ -88,7 +88,6 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
new_sig_a.sort_and_unify();
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
total_count++;