mirror of https://github.com/YosysHQ/yosys.git
Call internal checker more often
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223892ac28
commit
378cc509cd
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@ -856,6 +856,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
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if (design->modules.count(modname) == 0) {
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new_ast->str = modname;
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design->modules[modname] = process_module(new_ast);
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design->modules[modname]->check();
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} else {
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log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
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}
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@ -67,14 +67,10 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig
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if (f == NULL)
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log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno));
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std::string command;
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while (fgetline(f, command)) {
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while (fgetline(f, command))
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Pass::call(design, command);
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design->check();
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}
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if (!command.empty()) {
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if (!command.empty())
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Pass::call(design, command);
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design->check();
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}
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if (filename != "-")
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fclose(f);
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if (backend_command != NULL && *backend_command == "auto")
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@ -89,7 +85,6 @@ static void run_frontend(std::string filename, std::string command, RTLIL::Desig
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}
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Frontend::frontend_call(design, NULL, filename, command);
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design->check();
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}
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static void run_pass(std::string command, RTLIL::Design *design)
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@ -97,7 +92,6 @@ static void run_pass(std::string command, RTLIL::Design *design)
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log("\n-- Running pass `%s' --\n", command.c_str());
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Pass::call(design, command);
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design->check();
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}
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static void run_backend(std::string filename, std::string command, RTLIL::Design *design)
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@ -125,7 +119,6 @@ static void run_backend(std::string filename, std::string command, RTLIL::Design
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}
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Backend::backend_call(design, NULL, filename, command);
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design->check();
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}
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static char *readline_cmd_generator(const char *text, int state)
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@ -178,6 +178,8 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
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pass_register[args[0]]->execute(args, design);
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while (design->selection_stack.size() > orig_sel_stack_pos)
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design->selection_stack.pop_back();
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design->check();
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}
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Frontend::Frontend(std::string name, std::string short_help) : Pass("read_"+name, short_help), frontend_name(name)
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@ -270,6 +272,8 @@ void Frontend::frontend_call(RTLIL::Design *design, FILE *f, std::string filenam
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args.push_back(filename);
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frontend_register[args[0]]->execute(args, design);
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}
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design->check();
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}
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Backend::Backend(std::string name, std::string short_help) : Pass("write_"+name, short_help), backend_name(name)
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@ -364,6 +368,8 @@ void Backend::backend_call(RTLIL::Design *design, FILE *f, std::string filename,
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while (design->selection_stack.size() > orig_sel_stack_pos)
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design->selection_stack.pop_back();
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design->check();
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}
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struct HelpPass : public Pass {
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@ -352,6 +352,8 @@ struct TechmapPass : public Pass {
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for (auto &mod_it : design->modules)
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if (techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false, opt_mode))
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did_something = true;
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if (did_something)
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design->check();
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}
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log("No more expansions possible.\n");
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