riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Bugfix in "miter -assert" handling of assumptions

This commit is contained in:
Clifford Wolf 2016-10-17 14:56:58 +02:00
parent 6425d34e73
commit 15fb56697a
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/sat/miter.cc
View File

@ -338,12 +338,12 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
else
{
Wire *assume_q = module->addWire(NEW_ID);
assume_q->attributes["\\init"] = State::S1;
assume_q->attributes["\\init"] = State::S0;
assume_signals.append(assume_q);
SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
SigSpec assume_ok = module->Not(NEW_ID, assume_nok);
module->addFf(NEW_ID, assume_ok, assume_q);
module->addFf(NEW_ID, assume_nok, assume_q);
SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals);
module->addAnd(NEW_ID, assert_fail, assume_ok, trigger);