mirror of https://github.com/YosysHQ/yosys.git
Fixed undef handling in opt_reduce
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973507d85b
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@ -65,8 +65,8 @@ struct OptReduceWorker
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continue;
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}
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if (chunk.wire == NULL) {
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new_sig_a = RTLIL::SigSpec(RTLIL::State::Sx);
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break;
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new_sig_a.append(chunk);
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continue;
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}
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bool imported_children = false;
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