mirror of https://github.com/YosysHQ/yosys.git
Progress in memory_bram
This commit is contained in:
Clifford Wolf
parent
e62d838bd4
commit
17c1c55473
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@ -214,20 +214,41 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
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{
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auto portinfos = bram.make_portinfos();
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dict<int, pair<SigBit, bool>> clock_domains;
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vector<int> mapped_wr_ports;
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vector<int> mapped_wr_ports, mapped_rd_ports;
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dict<int, int> used_rd_ports;
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int rd_port_dups = 1;
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log(" Mapping to bram type %s:\n", log_id(bram.name));
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int wr_ports_n = cell->getParam("\\WR_PORTS").as_int();
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int mem_size = cell->getParam("\\SIZE").as_int();
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int mem_abits = cell->getParam("\\ABITS").as_int();
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int mem_width = cell->getParam("\\WIDTH").as_int();
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int mem_offset = cell->getParam("\\OFFSET").as_int();
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int wr_ports = cell->getParam("\\WR_PORTS").as_int();
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auto wr_clken = SigSpec(cell->getParam("\\WR_CLK_ENABLE"));
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auto wr_clkpol = SigSpec(cell->getParam("\\WR_CLK_POLARITY"));
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wr_clken.extend_u0(wr_ports_n);
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wr_clkpol.extend_u0(wr_ports_n);
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wr_clken.extend_u0(wr_ports);
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wr_clkpol.extend_u0(wr_ports);
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SigSpec wr_clk = cell->getPort("\\WR_CLK");
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SigSpec wr_en = cell->getPort("\\WR_EN");
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SigSpec wr_clk = cell->getPort("\\WR_CLK");
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SigSpec wr_data = cell->getPort("\\WR_DATA");
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SigSpec wr_addr = cell->getPort("\\WR_ADDR");
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for (int cell_port_i = 0, bram_port_i = 0; cell_port_i < wr_ports_n; cell_port_i++)
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int rd_ports = cell->getParam("\\RD_PORTS").as_int();
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auto rd_clken = SigSpec(cell->getParam("\\RD_CLK_ENABLE"));
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auto rd_clkpol = SigSpec(cell->getParam("\\RD_CLK_POLARITY"));
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auto rd_transp = SigSpec(cell->getParam("\\RD_TRANSPARENT"));
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rd_clken.extend_u0(rd_ports);
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rd_clkpol.extend_u0(rd_ports);
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rd_transp.extend_u0(rd_ports);
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SigSpec rd_clk = cell->getPort("\\RD_CLK");
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SigSpec rd_data = cell->getPort("\\RD_DATA");
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SigSpec rd_addr = cell->getPort("\\RD_ADDR");
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for (int cell_port_i = 0, bram_port_i = 0; cell_port_i < wr_ports; cell_port_i++)
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{
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bool clken = wr_clken[cell_port_i] == State::S1;
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auto clkpol = wr_clkpol[cell_port_i] == State::S1;
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@ -279,15 +300,84 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
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if (clken)
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clock_domains[pi.clocks] = clkdom;
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mapped_wr_ports.push_back(bram_port_i);
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goto mapped_port;
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goto mapped_wr_port;
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}
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log(" Failed to map write port #%d.\n", cell_port_i);
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log(" Failed to map write port #%d.\n", cell_port_i);
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return false;
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mapped_port:;
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mapped_wr_port:;
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}
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log(" FIXME: The core of memory_bram is not implemented yet.\n");
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int grow_read_ports_cursor = -1;
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bool try_growing_more_read_ports = false;
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if (0) {
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grow_read_ports:;
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rd_port_dups++;
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mapped_rd_ports.clear();
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used_rd_ports.clear();
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}
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for (int cell_port_i = 0; cell_port_i < rd_ports; cell_port_i++)
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{
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bool clken = rd_clken[cell_port_i] == State::S1;
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auto clkpol = rd_clkpol[cell_port_i] == State::S1;
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auto clksig = rd_clk[cell_port_i];
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pair<SigBit, bool> clkdom(clksig, clkpol);
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if (!clken)
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clkdom = pair<SigBit, bool>(State::S1, false);
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log(" Read port #%d is in clock domain %s%s.\n",
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cell_port_i, clkdom.second ? "" : "!",
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clken ? log_signal(clkdom.first) : "~async~");
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for (int bram_port_i = 0; bram_port_i < GetSize(portinfos); bram_port_i++)
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{
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auto &pi = portinfos[bram_port_i];
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if (pi.wrmode != 0 || used_rd_ports[bram_port_i] >= rd_port_dups)
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skip_bram_rport:
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continue;
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if (clken) {
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if (pi.clocks == 0) {
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log(" Bram port %c%d has incompatible clock type.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_rport;
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}
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if (clock_domains.count(pi.clocks) && clock_domains.at(pi.clocks) != clkdom) {
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log(" Bram port %c%d is in a different clock domain.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_rport;
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}
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} else {
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if (pi.clocks != 0) {
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log(" Bram port %c%d has incompatible clock type.\n", pi.group + 'A', pi.index + 1);
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goto skip_bram_rport;
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}
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}
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log(" Mapped to bram port %c%d.%d.\n", pi.group + 'A', pi.index + 1, used_rd_ports[bram_port_i] + 1);
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if (clken)
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clock_domains[pi.clocks] = clkdom;
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if (grow_read_ports_cursor < bram_port_i) {
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grow_read_ports_cursor = bram_port_i;
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try_growing_more_read_ports = true;
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}
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mapped_rd_ports.push_back(bram_port_i);
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used_rd_ports[bram_port_i]++;
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goto mapped_rd_port;
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}
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log(" Failed to map read port #%d.\n", cell_port_i);
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if (try_growing_more_read_ports) {
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log(" Growing more read ports by duplicating bram cells.\n");
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goto grow_read_ports;
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}
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return false;
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mapped_rd_port:;
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}
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log(" FIXME: The core of memory_bram is not implemented yet.\n");
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return false;
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}
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@ -295,17 +385,17 @@ void handle_cell(Cell *cell, const rules_t &rules)
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{
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log("Processing %s.%s:\n", log_id(cell->module), log_id(cell));
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dict<string, int> mem_properties;
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mem_properties["words"] = cell->getParam("\\SIZE").as_int();
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mem_properties["abits"] = cell->getParam("\\ABITS").as_int();
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mem_properties["dbits"] = cell->getParam("\\WIDTH").as_int();
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mem_properties["wports"] = cell->getParam("\\WR_PORTS").as_int();
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mem_properties["rports"] = cell->getParam("\\RD_PORTS").as_int();
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mem_properties["bits"] = mem_properties["words"] * mem_properties["dbits"];
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mem_properties["ports"] = mem_properties["wports"] + mem_properties["rports"];
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dict<string, int> match_properties;
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match_properties["words"] = cell->getParam("\\SIZE").as_int();
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match_properties["abits"] = cell->getParam("\\ABITS").as_int();
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match_properties["dbits"] = cell->getParam("\\WIDTH").as_int();
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match_properties["wports"] = cell->getParam("\\WR_PORTS").as_int();
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match_properties["rports"] = cell->getParam("\\RD_PORTS").as_int();
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match_properties["bits"] = match_properties["words"] * match_properties["dbits"];
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match_properties["ports"] = match_properties["wports"] + match_properties["rports"];
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log(" Properties:");
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for (auto &it : mem_properties)
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for (auto &it : match_properties)
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log(" %s=%d", it.first.c_str(), it.second);
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log("\n");
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@ -313,37 +403,55 @@ void handle_cell(Cell *cell, const rules_t &rules)
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for (int i = 0; i < GetSize(rules.matches); i++)
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{
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if (rules.matches[i].name.in(failed_brams))
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continue;
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for (auto it : rules.matches[i].min_limits) {
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if (!mem_properties.count(it.first))
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log_error("Unknown property '%s' in match rule for bram type %s.\n",
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it.first.c_str(), log_id(rules.matches[i].name));
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if (mem_properties[it.first] >= it.second)
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continue;
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log(" Rule #%d for bram type %s rejected: requirement 'min %s %d' not met.\n",
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i, log_id(rules.matches[i].name), it.first.c_str(), it.second);
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goto next_match_rule;
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}
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for (auto it : rules.matches[i].max_limits) {
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if (!mem_properties.count(it.first))
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log_error("Unknown property '%s' in match rule for bram type %s.\n",
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it.first.c_str(), log_id(rules.matches[i].name));
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if (mem_properties[it.first] <= it.second)
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continue;
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log(" Rule #%d for bram type %s rejected: requirement 'max %s %d' not met.\n",
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i, log_id(rules.matches[i].name), it.first.c_str(), it.second);
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goto next_match_rule;
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}
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log(" Rule #%d for bram type %s accepted.\n", i, log_id(rules.matches[i].name));
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if (!rules.brams.count(rules.matches[i].name))
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log_error("No bram description for resource %s found!\n", log_id(rules.matches[i].name));
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if (!replace_cell(cell, rules.brams.at(rules.matches[i].name), rules.matches[i])) {
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log(" Mapping to bram type %s failed.\n", log_id(rules.matches[i].name));
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failed_brams.insert(rules.matches[i].name);
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auto &match = rules.matches.at(i);
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auto &bram = rules.brams.at(match.name);
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if (match.name.in(failed_brams))
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continue;
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int aover = match_properties["words"] % (1 << bram.abits);
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int awaste = aover ? (1 << bram.abits) - aover : 0;
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match_properties["awaste"] = awaste;
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int dover = match_properties["dbits"] % bram.dbits;
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int dwaste = dover ? bram.dbits - dover : 0;
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match_properties["dwaste"] = dwaste;
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int waste = awaste * bram.dbits + dwaste * (1 << bram.abits) - awaste * dwaste;
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match_properties["waste"] = waste;
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log(" Wasted bits for bram type %s: awaste=%d dwaste=%d waste=%d\n",
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log_id(match.name), awaste, dwaste, waste);
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for (auto it : match.min_limits) {
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if (!match_properties.count(it.first))
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log_error("Unknown property '%s' in match rule for bram type %s.\n",
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it.first.c_str(), log_id(match.name));
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if (match_properties[it.first] >= it.second)
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continue;
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log(" Rule #%d for bram type %s rejected: requirement 'min %s %d' not met.\n",
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i, log_id(match.name), it.first.c_str(), it.second);
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goto next_match_rule;
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}
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for (auto it : match.max_limits) {
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if (!match_properties.count(it.first))
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log_error("Unknown property '%s' in match rule for bram type %s.\n",
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it.first.c_str(), log_id(match.name));
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if (match_properties[it.first] <= it.second)
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continue;
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log(" Rule #%d for bram type %s rejected: requirement 'max %s %d' not met.\n",
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i, log_id(match.name), it.first.c_str(), it.second);
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goto next_match_rule;
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}
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log(" Rule #%d for bram type %s accepted.\n", i, log_id(match.name));
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if (!replace_cell(cell, bram, match)) {
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log(" Mapping to bram type %s failed.\n", log_id(match.name));
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failed_brams.insert(match.name);
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goto next_match_rule;
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}
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return;
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