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Fixed inserting of Q-inverters in dfflibmap

This commit is contained in:
Clifford Wolf 2014-08-27 19:44:12 +02:00
parent cfb4338319
commit d148b0af0d
1 changed files with 5 additions and 0 deletions
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5
passes/techmap/dfflibmap.cc
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@ -409,6 +409,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
if ('A' <= port.second && port.second <= 'Z') {
sig = cell_connections[std::string("\\") + port.second];
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->addWire(NEW_ID, SIZE(old_sig));
module->addNotGate(NEW_ID, sig, old_sig);
} else
if ('a' <= port.second && port.second <= 'z') {
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->NotGate(NEW_ID, sig);