riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.

This commit is contained in:
Andrew Zonenberg 2017-09-04 21:49:56 -07:00
parent f9d023c53f
commit c4a70a8cc3
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/techmap/extract_counter.cc
View File

@ -424,12 +424,12 @@ void counter_worker(
cell->setPort("\\CLK", extract.clk);
cell->setPort("\\OUT", extract.outsig);
//Hook up hard-wired ports (for now CE and up/=down are not supported), default to no parallel output
//Hook up hard-wired ports (for now CE and up/down are not supported), default to no parallel output
cell->setParam("\\HAS_POUT", RTLIL::Const(0));
cell->setParam("\\HAS_CE", RTLIL::Const(0));
cell->setParam("\\DIRECTION", RTLIL::Const("DOWN"));
cell->setPort("\\CE", RTLIL::Const(1));
cell->setPort("\\UP", RTLIL::Const(1));
cell->setPort("\\UP", RTLIL::Const(0));
//Hook up any parallel outputs
for(auto load : extract.pouts)