mirror of https://github.com/YosysHQ/yosys.git
Various fixes/cleanups in alumacc and maccmap
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124e759280
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@ -443,7 +443,6 @@ struct AlumaccWorker
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n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
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n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
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n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
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log_cell(n->alu_cell);
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for (auto &it : n->cmp)
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{
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@ -208,7 +208,17 @@ struct MaccmapWorker
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log_assert(tree_sum_bits.empty());
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return module->Add(NEW_ID, summands.front(), summands.back());
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RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
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c->setPort("\\A", summands.front());
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c->setPort("\\B", summands.back());
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c->setPort("\\CI", RTLIL::S0);
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c->setPort("\\BI", RTLIL::S0);
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c->setPort("\\Y", module->addWire(NEW_ID, width));
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c->setPort("\\X", module->addWire(NEW_ID, width));
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c->setPort("\\CO", module->addWire(NEW_ID, width));
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c->fixup_parameters();
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return c->getPort("\\Y");
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}
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};
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