mirror of https://github.com/YosysHQ/yosys.git
Add "fmcombine -fwd -bwd -nop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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370db33a4c
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dacaebae35
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@ -24,15 +24,23 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct opts_t
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{
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bool fwd = false;
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bool bwd = false;
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bool nop = false;
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};
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struct FmcombineWorker
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{
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const opts_t &opts;
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Design *design;
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Module *original = nullptr;
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Module *module = nullptr;
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IdString orig_type, combined_type;
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FmcombineWorker(Design *design, IdString orig_type) :
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design(design), original(design->module(orig_type)),
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FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
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opts(opts), design(design), original(design->module(orig_type)),
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orig_type(orig_type), combined_type("$fmcombine" + orig_type.str())
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{
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}
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@ -63,7 +71,7 @@ struct FmcombineWorker
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if (!cell->parameters.empty())
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log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", log_id(original), log_id(cell));
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FmcombineWorker sub_worker(design, cell->type);
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FmcombineWorker sub_worker(design, cell->type, opts);
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sub_worker.generate();
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Cell *c = module->addCell(cell->name.str() + "_combined", sub_worker.combined_type);
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@ -106,6 +114,9 @@ struct FmcombineWorker
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module->connect(import_sig(conn.first, "_gate"), import_sig(conn.second, "_gate"));
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}
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if (opts.nop)
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return;
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CellTypes ct;
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ct.setup_internals_eval();
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ct.setup_stdcells_eval();
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@ -184,15 +195,19 @@ struct FmcombineWorker
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consequent = reduce_db.at(consequent);
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}
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module->addAssume(NEW_ID, consequent, antecedent);
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if (opts.fwd)
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module->addAssume(NEW_ID, consequent, antecedent);
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if (invert_db.count(antecedent) == 0)
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invert_db[antecedent] = module->Not(NEW_ID, antecedent);
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if (opts.bwd)
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{
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if (invert_db.count(antecedent) == 0)
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invert_db[antecedent] = module->Not(NEW_ID, antecedent);
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if (invert_db.count(consequent) == 0)
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invert_db[consequent] = module->Not(NEW_ID, consequent);
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if (invert_db.count(consequent) == 0)
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invert_db[consequent] = module->Not(NEW_ID, consequent);
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module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
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module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
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}
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}
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}
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}
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@ -214,9 +229,25 @@ struct FmcombinePass : public Pass {
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log("This is useful for formal test benches that check what differences in behavior\n");
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log("a slight difference in input causes in a module.\n");
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log("\n");
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log(" -fwd\n");
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log(" Insert forward hint assumptions into the combined module.\n");
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log("\n");
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log(" -bwd\n");
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log(" Insert backward hint assumptions into the combined module.\n");
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log(" (Backward hints are logically equivalend to fordward hits, but\n");
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log(" some solvers are faster with bwd hints, or even both -bwd and -fwd.)\n");
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log("\n");
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log(" -nop\n");
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log(" Don't insert hint assumptions into the combined module.\n");
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log(" (This should not provide any speedup over the original design, but\n");
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log(" strangely sometimes it does.)\n");
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log("\n");
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log("If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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opts_t opts;
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Module *module = nullptr;
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Cell *gold_cell = nullptr;
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Cell *gate_cell = nullptr;
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@ -230,6 +261,18 @@ struct FmcombinePass : public Pass {
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// filename = args[++argidx];
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// continue;
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// }
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if (args[argidx] == "-fwd") {
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opts.fwd = true;
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continue;
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}
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if (args[argidx] == "-bwd") {
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opts.bwd = true;
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continue;
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}
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if (args[argidx] == "-nop") {
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opts.nop = true;
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continue;
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}
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break;
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}
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if (argidx+2 == args.size())
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@ -262,6 +305,12 @@ struct FmcombinePass : public Pass {
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}
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// extra_args(args, argidx, design);
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if (opts.nop && (opts.fwd || opts.bwd))
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log_cmd_error("Option -nop can not be combined with -fwd and/or -bwd.\n");
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if (!opts.nop && !opts.fwd && !opts.bwd)
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opts.fwd = true;
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if (gold_cell->type != gate_cell->type)
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log_cmd_error("Types of gold and gate cells do not match.\n");
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if (!gold_cell->parameters.empty())
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@ -269,7 +318,7 @@ struct FmcombinePass : public Pass {
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if (!gate_cell->parameters.empty())
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log_cmd_error("Gold cell has unresolved instance parameters.\n");
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FmcombineWorker worker(design, gold_cell->type);
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FmcombineWorker worker(design, gold_cell->type, opts);
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worker.generate();
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IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", log_id(gold_cell), log_id(gate_cell)));
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