mirror of https://github.com/YosysHQ/yosys.git
Another small freduce cleanup/bugfix
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914e208aa3
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@ -482,7 +482,8 @@ struct FreduceWorker
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RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
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RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID);
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for (auto &port : drv->connections)
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sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
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if (ct.cell_output(drv->type, port.first))
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sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
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if (grp[i].inverted)
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{
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