mirror of https://github.com/YosysHQ/yosys.git
Added support for sr flip-flops to dfflibmap
This commit is contained in:
Clifford Wolf
parent
628b994cf6
commit
dd56004fc0
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@ -35,12 +35,14 @@ static void logmap(std::string dff)
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if (cell_mappings.count(dff) == 0) {
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log(" unmapped dff cell: %s\n", dff.c_str());
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} else {
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log(" %s %s(", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str());
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log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str());
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bool first = true;
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for (auto &port : cell_mappings[dff].ports) {
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char arg[3] = { port.second, 0, 0 };
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if ('a' <= arg[0] && arg[0] <= 'z')
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arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~';
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else
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arg[1] = arg[0], arg[0] = ' ';
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log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg);
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first = false;
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}
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@ -52,6 +54,7 @@ static void logmap_all()
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{
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logmap("$_DFF_N_");
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logmap("$_DFF_P_");
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logmap("$_DFF_NN0_");
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logmap("$_DFF_NN1_");
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logmap("$_DFF_NP0_");
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@ -60,6 +63,15 @@ static void logmap_all()
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logmap("$_DFF_PN1_");
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logmap("$_DFF_PP0_");
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logmap("$_DFF_PP1_");
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logmap("$_DFFSR_NNN_");
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logmap("$_DFFSR_NNP_");
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logmap("$_DFFSR_NPN_");
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logmap("$_DFFSR_NPP_");
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logmap("$_DFFSR_PNN_");
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logmap("$_DFFSR_PNP_");
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logmap("$_DFFSR_PPN_");
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logmap("$_DFFSR_PPP_");
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}
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static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, bool &pin_pol)
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@ -175,6 +187,88 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
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}
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}
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static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bool setpol, bool clrpol)
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{
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LibertyAst *best_cell = NULL;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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LibertyAst *ff = cell->find("ff");
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if (ff == NULL)
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continue;
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std::string cell_clk_pin, cell_set_pin, cell_clr_pin, cell_next_pin;
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bool cell_clk_pol, cell_set_pol, cell_clr_pol, cell_next_pol;
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if (!parse_pin(cell, ff->find("clocked_on"), cell_clk_pin, cell_clk_pol) || cell_clk_pol != clkpol)
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continue;
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if (!parse_pin(cell, ff->find("next_state"), cell_next_pin, cell_next_pol))
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continue;
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if (!parse_pin(cell, ff->find("preset"), cell_set_pin, cell_set_pol) || cell_set_pol != setpol)
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continue;
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if (!parse_pin(cell, ff->find("clear"), cell_clr_pin, cell_clr_pol) || cell_clr_pol != clrpol)
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continue;
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_clk_pin] = 'C';
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this_cell_ports[cell_set_pin] = 'S';
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this_cell_ports[cell_clr_pin] = 'R';
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this_cell_ports[cell_next_pin] = 'D';
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int num_pins = 0;
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bool found_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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LibertyAst *dir = pin->find("direction");
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if (dir == NULL || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != NULL) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if ((cell_next_pol == true && value == ff->args[0]) || (cell_next_pol == false && value == ff->args[1])) {
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this_cell_ports[pin->args[0]] = 'Q';
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != NULL && num_pins > best_cell_pins))
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != NULL) {
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log(" cell %s is a direct match for cell type %s.\n", best_cell->args[0].c_str(), cell_type.substr(1).c_str());
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cell_mappings[cell_type].cell_name = best_cell->args[0];
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static bool expand_cellmap_worker(std::string from, std::string to, std::string inv)
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{
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if (cell_mappings.count(to) > 0)
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@ -185,7 +279,10 @@ static bool expand_cellmap_worker(std::string from, std::string to, std::string
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports) {
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if (inv.find(it.second) == std::string::npos)
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char cmp_ch = it.second;
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if ('a' <= cmp_ch && cmp_ch <= 'z')
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cmp_ch -= 'a' - 'A';
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if (inv.find(cmp_ch) == std::string::npos)
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continue;
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if ('a' <= it.second && it.second <= 'z')
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it.second -= 'a' - 'A';
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@ -223,6 +320,48 @@ static bool expand_cellmap(std::string pattern, std::string inv)
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return return_status;
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}
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static void map_sr_to_arst(const char *from, const char *to)
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{
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if (cell_mappings.count(to) > 0)
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return;
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char from_clk_pol = from[8], from_set_pol = from[9], from_clr_pol = from[10];
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char to_clk_pol = to[6], to_rst_pol = to[7], to_rst_val = to[8];
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log_assert(from_clk_pol == to_clk_pol);
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log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);
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log(" create mapping for %s from mapping for %s.\n", to, from);
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cell_mappings[to].cell_name = cell_mappings[from].cell_name;
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cell_mappings[to].ports = cell_mappings[from].ports;
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for (auto &it : cell_mappings[to].ports)
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{
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bool is_set_pin = it.second == 'S' || it.second == 's';
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bool is_clr_pin = it.second == 'R' || it.second == 'r';
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if (!is_set_pin && !is_clr_pin)
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continue;
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if ((to_rst_val == '0' && is_set_pin) || (to_rst_val == '1' && is_clr_pin))
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{
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// this is the unused set/clr pin -- deactivate it
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if (is_set_pin)
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it.second = (from_set_pol == 'P') == (it.second == 'S') ? '0' : '1';
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else
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it.second = (from_clr_pol == 'P') == (it.second == 'R') ? '0' : '1';
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}
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else
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{
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// this is the used set/clr pin -- rename it to 'reset'
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if (it.second == 'S')
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it.second = 'R';
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if (it.second == 's')
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it.second = 'r';
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}
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}
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}
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static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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{
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log("Mapping DFF cells in module `%s':\n", module->name.c_str());
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@ -256,7 +395,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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inv_cell->connections[port.second == 'q' ? "\\A" : "\\Y"] = sig;
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module->cells[inv_cell->name] = inv_cell;
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module->wires[inv_wire->name] = inv_wire;
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}
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} else
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if (port.second == '0' || port.second == '1') {
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sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
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} else
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log_abort();
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new_cell->connections["\\" + port.first] = sig;
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}
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stats[stringf(" mapped %%d %s cells to %s cells.\n", cell->type.c_str(), new_cell->type.c_str())]++;
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@ -311,6 +454,7 @@ struct DfflibmapPass : public Pass {
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find_cell(libparser.ast, "$_DFF_N_", false, false, false, false);
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find_cell(libparser.ast, "$_DFF_P_", true, false, false, false);
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find_cell(libparser.ast, "$_DFF_NN0_", false, true, false, false);
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find_cell(libparser.ast, "$_DFF_NN1_", false, true, false, true);
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find_cell(libparser.ast, "$_DFF_NP0_", false, true, true, false);
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@ -320,6 +464,15 @@ struct DfflibmapPass : public Pass {
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find_cell(libparser.ast, "$_DFF_PP0_", true, true, true, false);
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find_cell(libparser.ast, "$_DFF_PP1_", true, true, true, true);
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find_cell_sr(libparser.ast, "$_DFFSR_NNN_", false, false, false);
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find_cell_sr(libparser.ast, "$_DFFSR_NNP_", false, false, true);
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find_cell_sr(libparser.ast, "$_DFFSR_NPN_", false, true, false);
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find_cell_sr(libparser.ast, "$_DFFSR_NPP_", false, true, true);
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find_cell_sr(libparser.ast, "$_DFFSR_PNN_", true, false, false);
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find_cell_sr(libparser.ast, "$_DFFSR_PNP_", true, false, true);
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find_cell_sr(libparser.ast, "$_DFFSR_PPN_", true, true, false);
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find_cell_sr(libparser.ast, "$_DFFSR_PPP_", true, true, true);
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bool keep_running = true;
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while (keep_running) {
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keep_running = false;
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@ -327,7 +480,19 @@ struct DfflibmapPass : public Pass {
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keep_running |= expand_cellmap("$_DFF_*??_", "C");
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keep_running |= expand_cellmap("$_DFF_?*?_", "R");
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keep_running |= expand_cellmap("$_DFF_??*_", "DQ");
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keep_running |= expand_cellmap("$_DFFSR_*??_", "C");
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keep_running |= expand_cellmap("$_DFFSR_?*?_", "S");
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keep_running |= expand_cellmap("$_DFFSR_??*_", "R");
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}
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map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN0_");
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map_sr_to_arst("$_DFFSR_NNN_", "$_DFF_NN1_");
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map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP0_");
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map_sr_to_arst("$_DFFSR_NPP_", "$_DFF_NP1_");
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map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN0_");
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map_sr_to_arst("$_DFFSR_PNN_", "$_DFF_PN1_");
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map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP0_");
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map_sr_to_arst("$_DFFSR_PPP_", "$_DFF_PP1_");
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log(" final dff cell mappings:\n");
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logmap_all();
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