mirror of https://github.com/YosysHQ/yosys.git
Continue support for ShregmapTechXilinx7Static
This commit is contained in:
Eddie Hung
parent
6ed15b7890
commit
72eda94a66
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@ -28,8 +28,9 @@ struct ShregmapTech
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virtual ~ShregmapTech() { }
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virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
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virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
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virtual bool analyze_first(const Cell* /*first_cell*/, const SigMap &/*sigmap*/) { return true; }
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
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virtual Cell* fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
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};
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struct ShregmapOptions
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@ -71,7 +72,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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return true;
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}
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
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virtual Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
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{
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auto D = cell->getPort("\\D");
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auto C = cell->getPort("\\C");
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@ -99,18 +100,61 @@ struct ShregmapTechXilinx7Static : ShregmapTech
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ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) override
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virtual bool analyze_first(const Cell* first_cell, const SigMap &sigmap) override
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{
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if (GetSize(taps) == 1)
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return taps[0] >= opts.minlen-1;
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if (taps.back() < opts.minlen-1)
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return false;
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if (first_cell->type.in("\\FDRE", "\\FDRE_1")) {
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bool is_R_inverted = false;
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if (first_cell->hasParam("\\IS_R_INVERTED"))
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is_R_inverted = first_cell->getParam("\\IS_R_INVERTED").as_bool();
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SigBit R = sigmap(first_cell->getPort("\\R"));
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if (R != RTLIL::S0 && R != RTLIL::S1)
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return false;
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if ((!is_R_inverted && R != RTLIL::S0) || (is_R_inverted && R != RTLIL::S1))
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return false;
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return true;
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}
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if (first_cell->type.in("\\FDSE", "\\FDSE_1")) {
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bool is_S_inverted = false;
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if (first_cell->hasParam("\\IS_S_INVERTED"))
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is_S_inverted = first_cell->getParam("\\IS_S_INVERTED").as_bool();
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SigBit S = sigmap(first_cell->getPort("\\S"));
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if (S != RTLIL::S0 && S != RTLIL::S1)
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return false;
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if ((!is_S_inverted && S != RTLIL::S0) || (is_S_inverted && S != RTLIL::S1))
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return false;
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return true;
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}
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if (first_cell->type.in("\\FDCE", "\\FDCE_1")) {
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bool is_CLR_inverted = false;
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if (first_cell->hasParam("\\IS_CLR_INVERTED"))
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is_CLR_inverted = first_cell->getParam("\\IS_CLR_INVERTED").as_bool();
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SigBit CLR = sigmap(first_cell->getPort("\\CLR"));
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if (CLR != RTLIL::S0 && CLR != RTLIL::S1)
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return false;
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if ((!is_CLR_inverted && CLR != RTLIL::S0) || (is_CLR_inverted && CLR != RTLIL::S1))
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return false;
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return true;
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}
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if (first_cell->type.in("\\FDPE", "\\FDPE_1")) {
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bool is_PRE_inverted = false;
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if (first_cell->hasParam("\\IS_PRE_INVERTED"))
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is_PRE_inverted = first_cell->getParam("\\IS_PRE_INVERTED").as_bool();
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SigBit PRE = sigmap(first_cell->getPort("\\PRE"));
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if (PRE != RTLIL::S0 && PRE != RTLIL::S1)
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return false;
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if ((!is_PRE_inverted && PRE != RTLIL::S0) || (is_PRE_inverted && PRE != RTLIL::S1))
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return false;
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return true;
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}
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return true;
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}
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &/*taps*/) override
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) override
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{
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return GetSize(taps) == 1 && taps[0] >= opts.minlen-1;
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}
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virtual Cell* fixup(Cell *cell, dict<int, SigBit> &/*taps*/) override
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{
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auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_");
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newcell->set_src_attribute(cell->get_src_attribute());
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@ -136,16 +180,17 @@ struct ShregmapTechXilinx7Static : ShregmapTech
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if (cell->hasPort("\\E"))
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newcell->setPort("\\E", cell->getPort("\\E"));
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}
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else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) {
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if (cell->getParam("\\IS_C_INVERTED").as_bool())
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newcell->setParam("\\CLKPOL", 0);
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else
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newcell->setParam("\\CLKPOL", 1);
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else if (cell->type.in("$__SHREG_FDRE", "$__SHREG_FDRE_1","$__SHREG_FDSE", "$__SHREG_FDSE_1",
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"$__SHREG_FDCE", "$__SHREG_FDCE_1", "$__SHREG_FDPE", "$__SHREG_FDPE_1")) {
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int param_clkpol = 1;
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if (cell->hasParam("\\IS_C_INVERTED") && cell->getParam("\\IS_C_INVERTED").as_bool())
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param_clkpol = 0;
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newcell->setParam("\\CLKPOL", param_clkpol);
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newcell->setParam("\\ENPOL", 1);
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newcell->setPort("\\E", cell->getPort("\\CE"));
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}
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else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) {
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else if (cell->type.in("$__SHREG_FDRE_1", "$__SHREG_FDSE_1", "$__SHREG_FDCE_1", "$__SHREG_FDPE_1")) {
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newcell->setParam("\\CLKPOL", 0);
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newcell->setPort("\\E", cell->getPort("\\CE"));
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@ -215,13 +260,14 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
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Cell *shiftx = nullptr;
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int group = 0;
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for (int i = 0; i < GetSize(taps); ++i) {
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// Check taps are sequential
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if (i != taps[i])
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return false;
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auto it = sigbit_to_shiftx_offset.find(qbits[i]);
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if (it == sigbit_to_shiftx_offset.end())
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return false;
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// Check taps are sequential
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if (i != taps[i])
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return false;
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// Check taps are not connected to a shift register,
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// or sequential to the same shift register
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if (i == 0) {
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@ -268,7 +314,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
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return true;
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}
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
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virtual Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
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{
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const auto &tap = *taps.begin();
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auto bit = tap.second;
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@ -276,7 +322,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
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auto it = sigbit_to_shiftx_offset.find(bit);
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log_assert(it != sigbit_to_shiftx_offset.end());
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RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps);
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Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps);
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log_assert(newcell);
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log_assert(newcell->type == "$__SHREG_");
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newcell->type = "$__XILINX_SHREG_";
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@ -451,6 +497,11 @@ struct ShregmapWorker
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if (opts.tech)
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{
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if (!opts.tech->analyze_first(first_cell, sigmap)) {
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cursor += depth;
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continue;
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}
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vector<SigBit> qbits;
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vector<int> taps;
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@ -724,16 +775,16 @@ struct ShregmapPass : public Pass {
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opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDRE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDSE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDCE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDPE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDRE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDSE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDCE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDPE"] = make_pair(IdString("\\D"), IdString("\\Q"));
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opts.ffcells["\\FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
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if (tech == "xilinx_static")
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opts.tech = new ShregmapTechXilinx7Dynamic(opts);
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opts.tech = new ShregmapTechXilinx7Static(opts);
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else if (tech == "xilinx_dynamic")
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opts.tech = new ShregmapTechXilinx7Dynamic(opts);
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} else {
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