mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #770 from whitequark/opt_expr_cmp
opt_expr: refactor and improve simplification of comparisons
This commit is contained in:
Clifford Wolf
GitHub
commit
0fc6e2bfcf
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@ -259,6 +259,22 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
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return last_bit_one;
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}
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int get_highest_hot_index(RTLIL::SigSpec signal)
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{
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for (int i = GetSize(signal) - 1; i >= 0; i--)
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{
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if (signal[i] == RTLIL::State::S0)
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continue;
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if (signal[i] == RTLIL::State::S1)
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return i;
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break;
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}
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return -1;
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}
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// if the signal has only one bit set, return the index of that bit.
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// otherwise return -1
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int get_onehot_bit_index(RTLIL::SigSpec signal)
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@ -1344,119 +1360,140 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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// replace a<0 or a>=0 with the top bit of a
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// simplify comparisons
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if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
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{
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//used to decide whether the signal needs to be negated
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bool is_lt = false;
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IdString cmp_type = cell->type;
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SigSpec var_sig = cell->getPort("\\A");
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SigSpec const_sig = cell->getPort("\\B");
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int var_width = cell->parameters["\\A_WIDTH"].as_int();
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int const_width = cell->parameters["\\B_WIDTH"].as_int();
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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//references the variable signal in the comparison
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RTLIL::SigSpec sigVar;
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//references the constant signal in the comparison
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RTLIL::SigSpec sigConst;
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// note that this signal must be constant for the optimization
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// to take place, but it is not checked beforehand.
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// If new passes are added, this signal must be checked for const-ness
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//width of the variable port
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int width;
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int const_width;
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bool var_signed;
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if (cell->type == "$lt" || cell->type == "$ge") {
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is_lt = cell->type == "$lt" ? 1 : 0;
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sigVar = cell->getPort("\\A");
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sigConst = cell->getPort("\\B");
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width = cell->parameters["\\A_WIDTH"].as_int();
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const_width = cell->parameters["\\B_WIDTH"].as_int();
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var_signed = cell->parameters["\\A_SIGNED"].as_bool();
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} else
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if (cell->type == "$gt" || cell->type == "$le") {
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is_lt = cell->type == "$gt" ? 1 : 0;
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sigVar = cell->getPort("\\B");
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sigConst = cell->getPort("\\A");
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width = cell->parameters["\\B_WIDTH"].as_int();
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const_width = cell->parameters["\\A_WIDTH"].as_int();
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var_signed = cell->parameters["\\B_SIGNED"].as_bool();
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} else
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log_abort();
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// replace a(signed) < 0 with the high bit of a
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if (sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true)
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if (!const_sig.is_fully_const())
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{
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RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
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a_prime[0] = sigVar[width - 1];
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if (is_lt) {
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log("Replacing %s cell `%s' (implementing X<0) with X[%d]: %s\n",
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log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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} else {
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log("Replacing %s cell `%s' (implementing X>=0) with ~X[%d]: %s\n",
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log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
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module->addNot(NEW_ID, a_prime, cell->getPort("\\Y"));
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module->remove(cell);
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}
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did_something = true;
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goto next_cell;
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} else
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if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
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std::swap(var_sig, const_sig);
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std::swap(var_width, const_width);
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if (cmp_type == "$gt")
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cmp_type = "$lt";
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else if (cmp_type == "$lt")
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cmp_type = "$gt";
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else if (cmp_type == "$ge")
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cmp_type = "$le";
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else if (cmp_type == "$le")
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cmp_type = "$ge";
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}
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if (const_sig.is_fully_def() && const_sig.is_fully_const())
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{
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if (sigConst.is_fully_zero()) {
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RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y")));
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if (is_lt) {
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log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
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log_id(cell->type), log_id(cell));
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a_prime[0] = RTLIL::State::S0;
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} else {
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log("Replacing %s cell `%s' (implementing unsigned X>=0) with constant true.\n",
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log_id(cell->type), log_id(cell));
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a_prime[0] = RTLIL::State::S1;
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std::string condition, replacement;
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SigSpec replace_sig(State::S0, GetSize(cell->getPort("\\Y")));
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bool replace = false;
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bool remove = false;
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if (!is_signed)
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{ /* unsigned */
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if (const_sig.is_fully_zero() && cmp_type == "$lt") {
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condition = "unsigned X<0";
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replacement = "constant 0";
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replace_sig[0] = State::S0;
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replace = true;
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}
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if (const_sig.is_fully_zero() && cmp_type == "$ge") {
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condition = "unsigned X>=0";
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replacement = "constant 1";
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replace_sig[0] = State::S1;
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replace = true;
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}
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if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$gt") {
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condition = "unsigned X>~0";
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replacement = "constant 0";
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replace_sig[0] = State::S0;
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replace = true;
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}
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if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$le") {
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condition = "unsigned X<=~0";
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replacement = "constant 1";
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replace_sig[0] = State::S1;
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replace = true;
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}
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int const_bit_hot = get_onehot_bit_index(const_sig);
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if (const_bit_hot >= 0 && const_bit_hot < var_width)
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{
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RTLIL::SigSpec var_high_sig(RTLIL::State::S0, var_width - const_bit_hot);
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for (int i = const_bit_hot; i < var_width; i++) {
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var_high_sig[i - const_bit_hot] = var_sig[i];
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}
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if (cmp_type == "$lt")
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{
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condition = stringf("unsigned X<%s", log_signal(const_sig));
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replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
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module->addLogicNot(NEW_ID, var_high_sig, cell->getPort("\\Y"));
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remove = true;
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}
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if (cmp_type == "$ge")
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{
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condition = stringf("unsigned X>=%s", log_signal(const_sig));
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replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
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module->addReduceOr(NEW_ID, var_high_sig, cell->getPort("\\Y"));
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remove = true;
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}
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}
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int const_bit_set = get_highest_hot_index(const_sig);
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if(const_bit_set >= var_width)
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{
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string cmp_name;
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if (cmp_type == "$lt" || cmp_type == "$le")
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{
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if (cmp_type == "$lt") cmp_name = "<";
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if (cmp_type == "$le") cmp_name = "<=";
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condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
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replacement = "constant 1";
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replace_sig[0] = State::S1;
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replace = true;
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}
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if (cmp_type == "$gt" || cmp_type == "$ge")
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{
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if (cmp_type == "$gt") cmp_name = ">";
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if (cmp_type == "$ge") cmp_name = ">=";
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condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
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replacement = "constant 0";
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replace_sig[0] = State::S0;
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replace = true;
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}
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}
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}
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else
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{ /* signed */
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if (const_sig.is_fully_zero() && cmp_type == "$lt")
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{
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condition = "signed X<0";
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replacement = stringf("X[%d]", var_width - 1);
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replace_sig[0] = var_sig[var_width - 1];
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replace = true;
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}
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if (const_sig.is_fully_zero() && cmp_type == "$ge")
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{
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condition = "signed X>=0";
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replacement = stringf("X[%d]", var_width - 1);
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module->addNot(NEW_ID, var_sig[var_width - 1], cell->getPort("\\Y"));
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remove = true;
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}
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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int const_bit_set = get_onehot_bit_index(sigConst);
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if (const_bit_set >= 0 && const_bit_set < width) {
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int bit_set = const_bit_set;
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RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set);
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for (int i = bit_set; i < width; i++) {
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a_prime[i - bit_set] = sigVar[i];
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}
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if (is_lt) {
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log("Replacing %s cell `%s' (implementing unsigned X<%s) with !X[%d:%d]: %s.\n",
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log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
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module->addLogicNot(NEW_ID, a_prime, cell->getPort("\\Y"));
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} else {
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log("Replacing %s cell `%s' (implementing unsigned X>=%s) with |X[%d:%d]: %s.\n",
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log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
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module->addReduceOr(NEW_ID, a_prime, cell->getPort("\\Y"));
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}
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if (replace || remove)
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{
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log("Replacing %s cell `%s' (implementing %s) with %s.\n",
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log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
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if (replace)
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module->connect(cell->getPort("\\Y"), replace_sig);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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else if(const_bit_set >= width && const_bit_set >= 0){
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RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
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if(is_lt){
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a_prime[0] = RTLIL::State::S1;
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log("Replacing %s cell `%s' (implementing unsigned X[%d:0] < %s[%d:0]) with constant 0.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
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}
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else{
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log("Replacing %s cell `%s' (implementing unsigned X[%d:0]>= %s[%d:0]) with constant 1.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
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}
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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}
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}
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@ -0,0 +1,40 @@
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module top(...);
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input [3:0] a;
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output o1_1 = 4'b0000 > a;
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output o1_2 = 4'b0000 <= a;
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output o1_3 = 4'b1111 < a;
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output o1_4 = 4'b1111 >= a;
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output o1_5 = a < 4'b0000;
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output o1_6 = a >= 4'b0000;
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output o1_7 = a > 4'b1111;
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output o1_8 = a <= 4'b1111;
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output o2_1 = 4'sb0000 > $signed(a);
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output o2_2 = 4'sb0000 <= $signed(a);
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output o2_3 = $signed(a) < 4'sb0000;
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output o2_4 = $signed(a) >= 4'sb0000;
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output o3_1 = 4'b0100 > a;
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output o3_2 = 4'b0100 <= a;
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output o3_3 = a < 4'b0100;
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output o3_4 = a >= 4'b0100;
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output o4_1 = 5'b10000 > a;
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output o4_2 = 5'b10000 >= a;
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output o4_3 = 5'b10000 < a;
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output o4_4 = 5'b10000 <= a;
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output o4_5 = a < 5'b10000;
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output o4_6 = a <= 5'b10000;
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output o4_7 = a > 5'b10000;
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output o4_8 = a >= 5'b10000;
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output o5_1 = 5'b10100 > a;
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output o5_2 = 5'b10100 >= a;
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output o5_3 = 5'b10100 < a;
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output o5_4 = 5'b10100 <= a;
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output o5_5 = a < 5'b10100;
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output o5_6 = a <= 5'b10100;
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output o5_7 = a > 5'b10100;
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output o5_8 = a >= 5'b10100;
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endmodule
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@ -0,0 +1,4 @@
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read_verilog opt_expr_cmp.v
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 0 t:$gt t:$ge t:$lt t:$le
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