Merge pull request #1143 from YosysHQ/clifford/fix1135

Add "pmux2shiftx -norange"
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Eddie Hung 2019-06-27 11:48:48 -07:00 committed by GitHub
commit 6c210e5813
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4 changed files with 37 additions and 7 deletions

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@ -21,6 +21,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
- Added "pmux2shiftx -norange"
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
- Fixed sign extension of unsized constants with 'bx and 'bz MSB

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@ -221,6 +221,9 @@ struct Pmux2ShiftxPass : public Pass {
log(" select strategy for one-hot encoded control signals\n");
log(" default: pmux\n");
log("\n");
log(" -norange\n");
log(" disable $sub inference for \"range decoders\"\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@ -230,6 +233,7 @@ struct Pmux2ShiftxPass : public Pass {
bool optimize_onehot = true;
bool verbose = false;
bool verbose_onehot = false;
bool norange = false;
log_header(design, "Executing PMUX2SHIFTX pass.\n");
@ -270,6 +274,10 @@ struct Pmux2ShiftxPass : public Pass {
verbose_onehot = true;
continue;
}
if (args[argidx] == "-norange") {
norange = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -559,7 +567,7 @@ struct Pmux2ShiftxPass : public Pass {
int this_inv_delta = this_maxval - this_minval;
bool this_inv = false;
if (this_delta != this_inv_delta)
if (!norange && this_delta != this_inv_delta)
this_inv = this_inv_delta < this_delta;
else if (this_maxval != this_inv_maxval)
this_inv = this_inv_maxval < this_maxval;
@ -574,7 +582,7 @@ struct Pmux2ShiftxPass : public Pass {
if (best_src_col < 0)
this_is_better = true;
else if (this_delta != best_delta)
else if (!norange && this_delta != best_delta)
this_is_better = this_delta < best_delta;
else if (this_maxval != best_maxval)
this_is_better = this_maxval < best_maxval;
@ -656,7 +664,7 @@ struct Pmux2ShiftxPass : public Pass {
// check density percentages
Const offset(State::S0, GetSize(sig));
if (absolute_density < min_density && range_density >= min_density)
if (!norange && absolute_density < min_density && range_density >= min_density)
{
offset = Const(min_choice, GetSize(sig));
log(" offset: %s\n", log_signal(offset));

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@ -32,3 +32,13 @@ module pmux2shiftx_test (
endcase
end
endmodule
module issue01135(input [7:0] i, output o);
always @*
case (i[6:3])
4: o <= i[0];
3: o <= i[2];
7: o <= i[3];
default: o <= 1'b0;
endcase
endmodule

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@ -1,4 +1,7 @@
read_verilog pmux2shiftx.v
design -save read
hierarchy -top pmux2shiftx_test
prep
design -save gold
@ -21,8 +24,16 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load gold
stat
#design -load gold
#stat
#
#design -load gate
#stat
design -load gate
stat
design -load read
hierarchy -top issue01135
proc
pmux2shiftx -norange
opt -full
select -assert-count 0 t:$shift*
select -assert-count 1 t:$pmux